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add instantiate module command #20

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merged 1 commit into from
Mar 27, 2017
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Yushiao
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@Yushiao Yushiao commented Mar 27, 2017

Add instantiate module command

Usage:

  1. Open command palette Ctrl+Shift+P and type System Verilog: Instantiate Module
  2. Choose file you want to instantiate and it will insert inst at cursor location

#17 split PR to 3 PRs (3/3)

@mshr-h
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mshr-h commented Mar 27, 2017

Ok.

@mshr-h mshr-h merged commit ce54c8b into mshr-h:master Mar 27, 2017
@Yushiao Yushiao deleted the instantiate-module branch March 27, 2017 10:30
@skazarynau
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I have for example 100 sv files. When I type System Verilog: Instantiate Module, I see only 5 of them. How can I choose one from the other 95 files?

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3 participants