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memory and peripheral power domains and fast interrupts (#122)
* Solved issue #96. Added 2 timers into the ao_peripheral_subsystem and 2 timers into the peripheral_subsystem. * Solved issues #16 and #95. Connected each interrupt to the assigned destination. * Fixed code after review. * Done a parse with Verible. * Solved issue #120. Added wake-up events to power_manager. * Fixed a bug in the interrupt mapping. * Added peripheral_subsystem power domain. * Fixed a bug in power_manager.sv. * Added ram power domains. * Fixed code after review. * Added automatic generation of ram blocks support. * Done a parse with Verible. * Fixed code after review. * Updated .gitignore. * Updated interrupt assignments as previously discussed. * Added core-v-mini-mcu.upf to .gitignore. * Modified .gitignore. * UP template comments and multilines commands. * Solved multi-lines and comments problems during tpl files generation. * Removed automatic generation for power_manager.c. * Updated sw to support fast interrupts. * Added CSR registers saving during core power-gating. * Updated Makefile. * Added example_power_gating_periph and example_power_gating_ram_blocks. * Done a parse with Verible. * Updated .gitignore. * Added plic wake-up event to power_manager. * Added initial version of fast_intr_ctrl module. * Improved fast_intr_ctrl module. * Fixed a bug in spi_host_example.c. * Added interrupt array to power_manager input. * Updated example_power_gating_core.c app. * Ordered interrupts in power_manager. * Added clear fast interrupt in power_manager.c. * Done a parse with Verible. * Solved issue #148. * Fixed a bug in power_manager.hjson.tpl. * Fixed a bug in power_manager.hjson.tpl. * Added iso counters. * Added other iso counters. * Done a parse with Verible. * minor SW updates * update fast interrupt * remove reset mem domain * Fixed a non-functional bug in interrupt handlers. * Improved power_manager.c. * Updated vertors.S. * Updated Makefile. Co-authored-by: Machetti Simone <machetti@eslsrv13.intranet.epfl.ch> Co-authored-by: Benoît Denkinger <benoit.denkinger@epfl.ch> Co-authored-by: davide schiavone <davide@openhwgroup.org>
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,156 @@ | ||
| upf_version 2.1 | ||
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| set_design_top core_v_mini_mcu | ||
| set_scope . | ||
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| <%text> | ||
| ##################### | ||
| ## POWER DOMAINS ## | ||
| ##################### | ||
| </%text>\ | ||
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| create_power_domain PD_TOP -include_scope | ||
| create_power_domain PD_CPU -elements {cpu_subsystem_i} | ||
| create_power_domain PD_PERIP_SUBS -elements {peripheral_subsystem_i} | ||
| % for bank in range(ram_numbanks): | ||
| create_power_domain PD_MEM_BANK_${bank} -elements {memory_subsystem_i/gen_sram[${bank}].ram_i} | ||
| % endfor | ||
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| <%text> | ||
| #################### | ||
| ## POWER STATES ## | ||
| #################### | ||
| </%text>\ | ||
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| add_power_state PD_TOP.primary -state TOP_ON <%text>\</%text> | ||
| {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}} | ||
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| add_power_state PD_CPU.primary -state CPU_ON <%text>\</%text> | ||
| {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}} | ||
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| add_power_state PD_CPU.primary -state CPU_OFF <%text>\</%text> | ||
| {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT | ||
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| add_power_state PD_PERIP_SUBS.primary -state PERIP_SUBS_ON <%text>\</%text> | ||
| {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}} | ||
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| add_power_state PD_PERIP_SUBS.primary -state PERIP_SUBS_OFF <%text>\</%text> | ||
| {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT | ||
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| % for bank in range(ram_numbanks): | ||
| add_power_state PD_MEM_BANK_${bank}.primary -state MEM_BANK_${bank}_ON <%text>\</%text> | ||
| {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}} | ||
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| add_power_state PD_MEM_BANK_${bank}.primary -state MEM_BANK_${bank}_OFF <%text>\</%text> | ||
| {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT | ||
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| % endfor | ||
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| <%text> | ||
| ################### | ||
| ## SUPPLY NETS ## | ||
| ################### | ||
| </%text>\ | ||
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| create_supply_port VDD -direction in | ||
| create_supply_port VSS -direction in | ||
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| create_supply_net VDD | ||
| create_supply_net VSS | ||
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| connect_supply_net VDD -ports VDD | ||
| connect_supply_net VSS -ports VSS | ||
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| create_supply_set PD_TOP.primary -function {power VDD} -function {ground VSS} -update | ||
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| create_supply_net VDD_CPU | ||
| create_supply_set PD_CPU.primary -function {power VDD_CPU} -function {ground VSS} -update | ||
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| create_supply_net VDD_PERIP_SUBS | ||
| create_supply_set PD_PERIP_SUBS.primary -function {power VDD_PERIP_SUBS} -function {ground VSS} -update | ||
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| % for bank in range(ram_numbanks): | ||
| create_supply_net VDD_MEM_BANK_${bank} | ||
| create_supply_set PD_MEM_BANK_${bank}.primary -function {power VDD_MEM_BANK_${bank}} -function {ground VSS} -update | ||
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| % endfor | ||
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| <%text> | ||
| ################ | ||
| ## SWITCHES ## | ||
| ################ | ||
| </%text>\ | ||
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| create_power_switch switch_PD_CPU <%text>\</%text> | ||
| -supply_set PD_TOP.primary <%text>\</%text> | ||
| -domain PD_CPU <%text>\</%text> | ||
| -input_supply_port {sw_in VDD} <%text>\</%text> | ||
| -output_supply_port {sw_out VDD_CPU} <%text>\</%text> | ||
| -control_port {sw_ctrl cpu_subsystem_powergate_switch} <%text>\</%text> | ||
| -on_state {on_state sw_in {sw_ctrl}} <%text>\</%text> | ||
| -off_state {off_state {!sw_ctrl}} | ||
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| create_power_switch switch_PD_PERIP_SUBS <%text>\</%text> | ||
| -supply_set PD_TOP.primary <%text>\</%text> | ||
| -domain PD_PERIP_SUBS <%text>\</%text> | ||
| -input_supply_port {sw_in VDD} <%text>\</%text> | ||
| -output_supply_port {sw_out VDD_PERIP_SUBS} <%text>\</%text> | ||
| -control_port {sw_ctrl peripheral_subsystem_powergate_switch} <%text>\</%text> | ||
| -on_state {on_state sw_in {sw_ctrl}} <%text>\</%text> | ||
| -off_state {off_state {!sw_ctrl}} | ||
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| % for bank in range(ram_numbanks): | ||
| create_power_switch switch_PD_MEM_BANK_${bank} <%text>\</%text> | ||
| -supply_set PD_TOP.primary <%text>\</%text> | ||
| -domain PD_MEM_BANK_${bank} <%text>\</%text> | ||
| -input_supply_port {sw_in VDD} <%text>\</%text> | ||
| -output_supply_port {sw_out VDD_MEM_BANK_${bank}} <%text>\</%text> | ||
| -control_port {sw_ctrl memory_subsystem_banks_powergate_switch[${bank}]} <%text>\</%text> | ||
| -on_state {on_state sw_in {sw_ctrl}} <%text>\</%text> | ||
| -off_state {off_state {!sw_ctrl}} | ||
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| % endfor | ||
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| <%text> | ||
| ################# | ||
| ## ISOLATION ## | ||
| ################# | ||
| </%text>\ | ||
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| set_isolation cpu_iso <%text>\</%text> | ||
| -domain PD_CPU <%text>\</%text> | ||
| -isolation_power_net VDD <%text>\</%text> | ||
| -isolation_ground_net VSS <%text>\</%text> | ||
| -isolation_signal cpu_subsystem_powergate_iso <%text>\</%text> | ||
| -isolation_sense low <%text>\</%text> | ||
| -clamp_value 0 <%text>\</%text> | ||
| -applies_to both <%text>\</%text> | ||
| -name_prefix cpu_iso_cell <%text>\</%text> | ||
| -location parent | ||
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| set_isolation perip_subs_iso <%text>\</%text> | ||
| -domain PD_PERIP_SUBS <%text>\</%text> | ||
| -isolation_power_net VDD <%text>\</%text> | ||
| -isolation_ground_net VSS <%text>\</%text> | ||
| -isolation_signal peripheral_subsystem_powergate_iso <%text>\</%text> | ||
| -isolation_sense low <%text>\</%text> | ||
| -clamp_value 0 <%text>\</%text> | ||
| -applies_to both <%text>\</%text> | ||
| -name_prefix cpu_iso_cell <%text>\</%text> | ||
| -location parent | ||
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| % for bank in range(ram_numbanks): | ||
| set_isolation mem_bank_${bank}_iso <%text>\</%text> | ||
| -domain PD_MEM_BANK_${bank} <%text>\</%text> | ||
| -isolation_power_net VDD <%text>\</%text> | ||
| -isolation_ground_net VSS <%text>\</%text> | ||
| -isolation_signal memory_subsystem_banks_powergate_iso[${bank}] <%text>\</%text> | ||
| -isolation_sense low <%text>\</%text> | ||
| -clamp_value 0 <%text>\</%text> | ||
| -applies_to both <%text>\</%text> | ||
| -name_prefix cpu_iso_cell <%text>\</%text> | ||
| -location parent | ||
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| % endfor |
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