Fix fpga pins for two SPIs (#145)

Co-authored-by: rurodrig <ruben.rodriguezalvarez@epfl.ch>

hw/fpga/constraints/pynq-z2/constraints.xdc

@@ -1 +1 @@
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets core_v_mini_mcu_i/pad_ring_i/pad_cell_tck_i/xilinx_iobuf_i/O]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets core_v_mini_mcu_i/pad_ring_i/pad_clk_i/pad_out_o]

hw/fpga/constraints/pynq-z2/pin_assign.xdc

@@ -21,15 +21,21 @@ set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports boot_select_
 # Q2 / nWP
 # Q3 / nHLD
 
-set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports spi_csb_o]
-set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports spi_sck_o]
-set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[0]}]
-set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[1]}]
-set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[2]}]
-set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[3]}]
+set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
+set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
+set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
+set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
 #set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {crst}]
 set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
 
+set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb_o]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck_o]
+set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[0]}]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[1]}]
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[2]}]
+set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[3]}]
 
 ## Pmodb
 set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]

hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv

@@ -37,6 +37,10 @@ module xilinx_core_v_mini_mcu_wrapper
     output logic exit_value_o,
     inout  logic exit_valid_o,
 
+    inout logic [3:0] spi_flash_sd_io,
+    inout logic spi_flash_csb_o,
+    inout logic spi_flash_sck_o,
+
     inout logic [3:0] spi_sd_io,
     inout logic spi_csb_o,
     inout logic spi_sck_o,
@@ -49,6 +53,7 @@ module xilinx_core_v_mini_mcu_wrapper
   wire                                clk_gen;
   logic [                       31:0] exit_value;
   logic [spi_host_reg_pkg::NumCS-1:0] spi_csb;
+  logic [spi_host_reg_pkg::NumCS-1:0] spi_flash_csb;
   wire                                rst_n;
   logic [ CLK_LED_COUNT_LENGTH - 1:0] clk_count;
 
@@ -105,6 +110,10 @@ module xilinx_core_v_mini_mcu_wrapper
       .execute_from_flash_i(execute_from_flash_i),
       .boot_select_i(boot_select_i),
 
+      .spi_flash_sd_io(spi_flash_sd_io),
+      .spi_flash_csb_o(spi_flash_csb),
+      .spi_flash_sck_o(spi_flash_sck_o),
+
       .spi_sd_io(spi_sd_io),
       .spi_csb_o(spi_csb),
       .spi_sck_o(spi_sck_o),
@@ -117,6 +126,7 @@ module xilinx_core_v_mini_mcu_wrapper
   );
 
   assign exit_value_o = exit_value[0];
+  assign spi_flash_csb_o = spi_flash_csb[0];
   assign spi_csb_o = spi_csb[0];
 
 endmodule