[do not merge] example to break verible #16
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simone-machetti
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Sep 8, 2022
…o the assigned destination.
davideschiavone
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Oct 13, 2022
* Solved issue #96. Added 2 timers into the ao_peripheral_subsystem and 2 timers into the peripheral_subsystem. * Solved issues #16 and #95. Connected each interrupt to the assigned destination. * Fixed code after review. * Done a parse with Verible. * Solved issue #120. Added wake-up events to power_manager. * Fixed a bug in the interrupt mapping. * Added peripheral_subsystem power domain. * Fixed a bug in power_manager.sv. * Added ram power domains. * Fixed code after review. * Added automatic generation of ram blocks support. * Done a parse with Verible. * Fixed code after review. * Updated .gitignore. * Updated interrupt assignments as previously discussed. * Added core-v-mini-mcu.upf to .gitignore. * Modified .gitignore. * UP template comments and multilines commands. * Solved multi-lines and comments problems during tpl files generation. * Removed automatic generation for power_manager.c. * Updated sw to support fast interrupts. * Added CSR registers saving during core power-gating. * Updated Makefile. * Added example_power_gating_periph and example_power_gating_ram_blocks. * Done a parse with Verible. * Updated .gitignore. * Added plic wake-up event to power_manager. * Added initial version of fast_intr_ctrl module. * Improved fast_intr_ctrl module. * Fixed a bug in spi_host_example.c. * Added interrupt array to power_manager input. * Updated example_power_gating_core.c app. * Ordered interrupts in power_manager. * Added clear fast interrupt in power_manager.c. * Done a parse with Verible. * Solved issue #148. * Fixed a bug in power_manager.hjson.tpl. * Fixed a bug in power_manager.hjson.tpl. * Added iso counters. * Added other iso counters. * Done a parse with Verible. * minor SW updates * update fast interrupt * remove reset mem domain * Fixed a non-functional bug in interrupt handlers. * Improved power_manager.c. * Updated vertors.S. * Updated Makefile. Co-authored-by: Machetti Simone <machetti@eslsrv13.intranet.epfl.ch> Co-authored-by: Benoît Denkinger <benoit.denkinger@epfl.ch> Co-authored-by: davide schiavone <davide@openhwgroup.org>
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