-
Notifications
You must be signed in to change notification settings - Fork 4.3k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add storing of invalid ROC number error (errorType=36) in pixel GPU code #43052
Add storing of invalid ROC number error (errorType=36) in pixel GPU code #43052
Conversation
+code-checks Logs: https://cmssdt.cern.ch/SDT/code-checks/cms-sw-PR-43052/37253
|
A new Pull Request was created by @ferencek (Dinko F.) for master. It involves the following packages:
@cmsbuild, @jfernan2, @mandrenguyen can you please review it and eventually sign? Thanks. cms-bot commands are listed here |
enable gpu |
please test |
-1 Failed Tests: RelVals-GPU RelVals-GPU
Comparison SummarySummary:
|
please test |
+1 Summary: https://cmssdt.cern.ch/SDT/jenkins-artifacts/pull-request-integration/PR-a215df/35337/summary.html Comparison SummarySummary:
GPU Comparison SummarySummary:
|
+1 |
This pull request is fully signed and it will be integrated in one of the next master IBs (tests are also fine). This pull request will now be reviewed by the release team before it's merged. @sextonkennedy, @antoniovilela, @rappoccio (and backports should be raised in the release meeting by the corresponding L2) |
+1 |
PR description:
This is the latest in the series of PRs addressing imbalance in pixel FED errors in the GPU and CPU codes. After #42977 or, to be more precise, its 13_2_X backport #42978 was deployed in HI data taking, a remaining tiny mismatch concerning
errorType=36
(invalid ROC number) was observed in online DQM for run 375202. The origin of this mismatch was traced to the this CPU code block handlingerrorType=36
that does not have its equivalent in the GPU code. This missing piece in the GPU is added in this PR.PR validation:
To test the PR a single event where an error of type 36 occurs was picked from
/HIExpressPhysics/HIRun2023A-Express-v2/FEVT
(Run 375202, Event 158786571, LumiSection 177
) and a modified version of wf 141.008583 was run on it. Before this PR the DQM plot theSiPixelHeterogeneous/PixelErrorCompareGPUvsCPU/FEErrorVsFEDIdUnbalance
shows a mismatchand with the PR applied the mismatch is gone
This errors is fairly rare and it required processing close to 250k events from run 375202 in
/HIExpressPhysics/HIRun2023A-Express-v2/FEVT
to find the first occurrence of this error.If this PR is a backport please specify the original PR and why you need to backport that PR. If this PR will be backported please specify to which release cycle the backport is meant for:
Backport to 13_2_X planned.