Bump versions; cherry pick 9d99750 from master.

Revert staged generator PRs (#2329)

* Revert "updating README examples with Make changes (#2322)"

This reverts commit 875dcd3.

* Revert "fixing aspect generation (#2309)"

This reverts commit bbeb257.

* Revert "separate generator behavior into phases (#2274)"

This reverts commit 9d99750.

(cherry picked from commit e170f8f)

Makefrag

@@ -6,14 +6,9 @@ endif
 MODEL ?= TestHarness
 PROJECT ?= freechips.rocketchip.system
 CFG_PROJECT ?= $(PROJECT)
-CONFIG ?= $(CFG_PROJECT).DefaultConfig
+CONFIG ?= DefaultConfig
 # TODO: For now must match rocketchip.Generator
-comma := ,
-space := $() $()
-splitConfigs := $(subst $(comma), ,$(CONFIG))
-configBases := $(foreach config,$(splitConfigs),$(lastword $(subst ., ,$(config))))
-CONFIG_STR := $(subst $(space),_,$(configBases))
-long_name = $(PROJECT).$(CONFIG_STR)
+long_name = $(PROJECT).$(CONFIG)
 
 VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
 

README.md

@@ -284,25 +284,14 @@ Chisel generated Verilog code and its associated C++ code generated by
 Verilator.
 
     $ ls $ROCKETCHIP/emulator/generated-src
+    DefaultConfig.dts
+    DefaultConfig.graphml
+    DefaultConfig.json
+    DefaultConfig.memmap.json
     freechips.rocketchip.system.DefaultConfig
-    freechips.rocketchip.system.DefaultConfig.0x0.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0x0.1.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0x2000000.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0x40.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0xc000000.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.anno.json
-    freechips.rocketchip.system.DefaultConfig.behav_srams.v
-    freechips.rocketchip.system.DefaultConfig.conf
     freechips.rocketchip.system.DefaultConfig.d
-    freechips.rocketchip.system.DefaultConfig.dts
     freechips.rocketchip.system.DefaultConfig.fir
-    freechips.rocketchip.system.DefaultConfig.graphml
-    freechips.rocketchip.system.DefaultConfig.json
-    freechips.rocketchip.system.DefaultConfig.memmap.json
-    freechips.rocketchip.system.DefaultConfig.plusArgs
-    freechips.rocketchip.system.DefaultConfig.rom.conf
     freechips.rocketchip.system.DefaultConfig.v
-    TestHarness.anno.json
     $ ls $ROCKETCHIP/emulator/generated-src/freechips.rocketchip.system.DefaultConfig
     VTestHarness__1.cpp
     VTestHarness__2.cpp
@@ -334,7 +323,7 @@ writeback stage, perhaps, because of a instruction cache miss at PC
 You can generate synthesizable Verilog with the following commands:
 
     $ cd $ROCKETCHIP/vsim
-    $ make verilog CONFIG=freechips.rocketchip.system.DefaultFPGAConfig
+    $ make verilog CONFIG=DefaultFPGAConfig
 
 The Verilog used for the FPGA tools will be generated in
 vsim/generated-src. Please proceed further with the directions shown in
@@ -348,7 +337,7 @@ tests and benchmarks in simulation with the following commands
 (again assuming you have N cores on your host machine):
 
     $ cd $ROCKETCHIP/vsim
-    $ make -jN run CONFIG=freechips.rocketchip.system.DefaultFPGAConfig
+    $ make -jN run CONFIG=DefaultFPGAConfig
 
 The generated output looks similar to those generated from the emulator.
 Look into vsim/output/\*.out for the output of the executed assembly
@@ -365,25 +354,15 @@ Now take a look at vsim/generated-src, and the contents of the
 Top.DefaultConfig.conf file:
 
     $ cd $ROCKETCHIP/vsim/generated-src
-    freechips.rocketchip.system.DefaultConfig
-    freechips.rocketchip.system.DefaultConfig.0x0.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0x0.1.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0x2000000.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0x40.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.0xc000000.0.regmap.json
-    freechips.rocketchip.system.DefaultConfig.anno.json
+    DefaultConfig.dts
+    DefaultConfig.graphml
+    DefaultConfig.json
+    DefaultConfig.memmap.json
     freechips.rocketchip.system.DefaultConfig.behav_srams.v
     freechips.rocketchip.system.DefaultConfig.conf
     freechips.rocketchip.system.DefaultConfig.d
-    freechips.rocketchip.system.DefaultConfig.dts
     freechips.rocketchip.system.DefaultConfig.fir
-    freechips.rocketchip.system.DefaultConfig.graphml
-    freechips.rocketchip.system.DefaultConfig.json
-    freechips.rocketchip.system.DefaultConfig.memmap.json
-    freechips.rocketchip.system.DefaultConfig.plusArgs
-    freechips.rocketchip.system.DefaultConfig.rom.conf
     freechips.rocketchip.system.DefaultConfig.v
-    TestHarness.anno.json
     $ cat $ROCKETCHIP/vsim/generated-src/*.conf
     name data_arrays_0_ext depth 512 width 256 ports mrw mask_gran 8
     name tag_array_ext depth 64 width 88 ports mrw mask_gran 22
@@ -416,26 +395,26 @@ tests and benchmarks.
 ## <a name="param"></a> How can I parameterize my Rocket chip?
 
 By now, you probably figured out that all generated files have a configuration
-name attached, e.g. `freechips.rocketchip.system.DefaultConfig`. Take a look at
-`src/main/scala/system/Configs.scala`. Search for `NSets` and `NWays` defined in
-`BaseConfig`. You can change those numbers to get a Rocket core with different
+name attached, e.g. DefaultConfig. Take a look at
+src/main/scala/system/Configs.scala. Search for NSets and NWays defined in
+BaseConfig. You can change those numbers to get a Rocket core with different
 cache parameters. For example, by changing L1I, NWays to 4, you will get
 a 32KB 4-way set-associative L1 instruction cache rather than a 16KB 2-way
 set-associative L1 instruction cache.
-Towards the end, you can also find that `DefaultSmallConfig` inherits all
-parameters from `BaseConfig` but overrides the same parameters of
-`WithNSmallCores`.
+Towards the end, you can also find that DefaultSmallConfig inherits all
+parameters from BaseConfig but overrides the same parameters of
+WithNSmallCores.
 
-Now take a look at `vsim/Makefile`. Search for the `CONFIG` variable.
-By default, it is set to `freechips.rocketchip.system.DefaultConfig`.  You can also change the
+Now take a look at vsim/Makefile. Search for the CONFIG variable.
+By default, it is set to DefaultConfig.  You can also change the
 CONFIG variable on the make command line:
 
     $ cd $ROCKETCHIP/vsim
-    $ make -jN CONFIG=freechips.rocketchip.system.DefaultSmallConfig run-asm-tests
+    $ make -jN CONFIG=DefaultSmallConfig run-asm-tests
 
 Or, even by defining CONFIG as an environment variable:
 
-    $ export CONFIG=freechips.rocketchip.system.DefaultSmallConfig
+    $ export CONFIG=DefaultSmallConfig
     $ make -jN run-asm-tests
 
 This parameterization is one of the many strengths of processor
@@ -452,7 +431,7 @@ you can create your own Configuration(s) and compose them with Config's ++ opera
     }
     class MyConfig extends Config (new WithNExtInterrupts(16) ++ new DefaultSmallConfig)
 
-Then you can build as usual with `CONFIG=<MyConfigPackage>.MyConfig`.
+Then you can build as usual with CONFIG=MyConfig.
 
 ## <a name="debug"></a> Debugging with GDB
 
@@ -471,11 +450,11 @@ For that we need to add a Remote Bit-Bang client to the emulator. We can do so b
 To build the emulator with `DefaultConfigRBB` configuration we use the command:
 
     rocket-chip$ cd emulator
-    emulator$ CONFIG=freechips.rocketchip.system.DefaultConfigRBB make
+    emulator$ CONFIG=DefaultConfigRBB make
 
 We can also build a debug version capable of generating VCD waveforms using the command:
 
-    emulator$ CONFIG=freechips.rocketchip.system.DefaultConfigRBB make debug
+    emulator$ CONFIG=DefaultConfigRBB make debug
 
 By default the emulator is generated under the name `emulator-freechips.rocketchip.system-DefaultConfigRBB` in the first case and `emulator-freechips.rocketchip.system-DefaultConfigRBB-debug` in the second.
 

build.sbt

@@ -1,7 +1,9 @@
 // See LICENSE.Berkeley for license details.
 
+import sbt.complete._
 import sbt.complete.DefaultParsers._
-import scala.sys.process._
+import xerial.sbt.pack._
+import sys.process._
 
 enablePlugins(PackPlugin)
 
@@ -15,7 +17,6 @@ lazy val commonSettings = Seq(
   scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
   libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
   libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.6.1"),
-  libraryDependencies ++= Seq("org.scalatest" %% "scalatest" % "3.0.8" % "test"),
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),

emulator/Makefrag-verilator

@@ -10,7 +10,7 @@ verilog = \
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
 %.v %.conf: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
@@ -69,7 +69,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   --threads $(VERILATOR_THREADS) -Wno-UNOPTTHREADS \
 	-Wno-STMTDLY --x-assign unique \
   -I$(vsrc) \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(csrc)/verilator.h -include $(generated_dir)/$(long_name).plusArgs"
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(csrc)/verilator.h -include $(generated_dir)/$(PROJECT).$(CONFIG).plusArgs"
 cppfiles = $(addprefix $(csrc)/, $(addsuffix .cc, $(CXXSRCS)))
 headers = $(wildcard $(csrc)/*.h)
 

regression/Makefile

@@ -46,36 +46,36 @@ endif
 
 ifeq ($(SUITE),RocketSuiteA)
 PROJECT=freechips.rocketchip.system
-CONFIGS=$(PROJECT).DefaultConfig
+CONFIGS=DefaultConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteB)
 PROJECT=freechips.rocketchip.system
-CONFIGS=$(PROJECT).DefaultBufferlessConfig
+CONFIGS=DefaultBufferlessConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteC)
 PROJECT=freechips.rocketchip.system
-CONFIGS=$(PROJECT).TinyConfig
+CONFIGS=TinyConfig
 endif
 
 ifeq ($(SUITE),UnittestSuite)
 PROJECT=freechips.rocketchip.unittest
-CONFIGS=$(PROJECT).AMBAUnitTestConfig $(PROJECT).TLSimpleUnitTestConfig $(PROJECT).TLWidthUnitTestConfig
+CONFIGS=AMBAUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig
 endif
 
 ifeq ($(SUITE), JtagDtmSuite)
 PROJECT=freechips.rocketchip.system
 
 export JTAG_DTM_ENABLE_SBA ?= off
 ifeq ($(JTAG_DTM_ENABLE_SBA), off)
-CONFIGS_32=$(PROJECT).WithJtagDTMSystem,$(PROJECT).DefaultRV32Config
-CONFIGS_64=$(PROJECT).WithJtagDTMSystem,$(PROJECT).DefaultConfig
+CONFIGS_32=WithJtagDTMSystem_DefaultRV32Config
+CONFIGS_64=WithJtagDTMSystem_DefaultConfig
 endif
 
 ifeq ($(JTAG_DTM_ENABLE_SBA), on)
-CONFIGS_32=$(PROJECT).WithJtagDTMSystem,$(PROJECT).WithDebugSBASystem,$(PROJECT).DefaultRV32Config
-CONFIGS_64=$(PROJECT).WithJtagDTMSystem,$(PROJECT).WithDebugSBASystem,$(PROJECT).DefaultConfig
+CONFIGS_32=WithJtagDTMSystem_WithDebugSBASystem_DefaultRV32Config
+CONFIGS_64=WithJtagDTMSystem_WithDebugSBASystem_DefaultConfig
 endif
 
 CONFIGS += $(CONFIGS_32)
@@ -89,18 +89,18 @@ endif
 ifeq ($(SUITE), Miscellaneous)
 PROJECT=freechips.rocketchip.system
 CONFIGS=\
-	$(PROJECT).DefaultSmallConfig \
-	$(PROJECT).DualBankConfig \
-	$(PROJECT).DualChannelConfig \
-	$(PROJECT).DualChannelDualBankConfig \
-	$(PROJECT).RoccExampleConfig \
-	$(PROJECT).Edge128BitConfig \
-	$(PROJECT).Edge32BitConfig \
-	$(PROJECT).QuadChannelBenchmarkConfig \
-	$(PROJECT).EightChannelConfig \
-	$(PROJECT).DualCoreConfig \
-	$(PROJECT).MemPortOnlyConfig \
-	$(PROJECT).MMIOPortOnlyConfig
+	DefaultSmallConfig \
+	DualBankConfig \
+	DualChannelConfig \
+	DualChannelDualBankConfig \
+	RoccExampleConfig \
+	Edge128BitConfig \
+	Edge32BitConfig \
+	QuadChannelBenchmarkConfig \
+	EightChannelConfig \
+	DualCoreConfig \
+	MemPortOnlyConfig \
+	MMIOPortOnlyConfig
 endif
 
 # These are the named regression targets.  While it's expected you run them in

src/main/scala/groundtest/Generator.scala

@@ -2,7 +2,11 @@
 
 package freechips.rocketchip.groundtest
 
-import firrtl.options.StageMain
-import freechips.rocketchip.system.RocketChipStage
+import freechips.rocketchip.util.GeneratorApp
 
-object Generator extends StageMain(new RocketChipStage)
+object Generator extends GeneratorApp {
+  generateFirrtl
+  generateAnno
+  generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
+  generateArtefacts
+}