updating README examples with Make changes (#2322)

README.md

@@ -284,14 +284,25 @@ Chisel generated Verilog code and its associated C++ code generated by
 Verilator.
 
     $ ls $ROCKETCHIP/emulator/generated-src
-    DefaultConfig.dts
-    DefaultConfig.graphml
-    DefaultConfig.json
-    DefaultConfig.memmap.json
     freechips.rocketchip.system.DefaultConfig
+    freechips.rocketchip.system.DefaultConfig.0x0.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0x0.1.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0x2000000.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0x40.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0xc000000.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.anno.json
+    freechips.rocketchip.system.DefaultConfig.behav_srams.v
+    freechips.rocketchip.system.DefaultConfig.conf
     freechips.rocketchip.system.DefaultConfig.d
+    freechips.rocketchip.system.DefaultConfig.dts
     freechips.rocketchip.system.DefaultConfig.fir
+    freechips.rocketchip.system.DefaultConfig.graphml
+    freechips.rocketchip.system.DefaultConfig.json
+    freechips.rocketchip.system.DefaultConfig.memmap.json
+    freechips.rocketchip.system.DefaultConfig.plusArgs
+    freechips.rocketchip.system.DefaultConfig.rom.conf
     freechips.rocketchip.system.DefaultConfig.v
+    TestHarness.anno.json
     $ ls $ROCKETCHIP/emulator/generated-src/freechips.rocketchip.system.DefaultConfig
     VTestHarness__1.cpp
     VTestHarness__2.cpp
@@ -323,7 +334,7 @@ writeback stage, perhaps, because of a instruction cache miss at PC
 You can generate synthesizable Verilog with the following commands:
 
     $ cd $ROCKETCHIP/vsim
-    $ make verilog CONFIG=DefaultFPGAConfig
+    $ make verilog CONFIG=freechips.rocketchip.system.DefaultFPGAConfig
 
 The Verilog used for the FPGA tools will be generated in
 vsim/generated-src. Please proceed further with the directions shown in
@@ -337,7 +348,7 @@ tests and benchmarks in simulation with the following commands
 (again assuming you have N cores on your host machine):
 
     $ cd $ROCKETCHIP/vsim
-    $ make -jN run CONFIG=DefaultFPGAConfig
+    $ make -jN run CONFIG=freechips.rocketchip.system.DefaultFPGAConfig
 
 The generated output looks similar to those generated from the emulator.
 Look into vsim/output/\*.out for the output of the executed assembly
@@ -354,15 +365,25 @@ Now take a look at vsim/generated-src, and the contents of the
 Top.DefaultConfig.conf file:
 
     $ cd $ROCKETCHIP/vsim/generated-src
-    DefaultConfig.dts
-    DefaultConfig.graphml
-    DefaultConfig.json
-    DefaultConfig.memmap.json
+    freechips.rocketchip.system.DefaultConfig
+    freechips.rocketchip.system.DefaultConfig.0x0.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0x0.1.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0x2000000.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0x40.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.0xc000000.0.regmap.json
+    freechips.rocketchip.system.DefaultConfig.anno.json
     freechips.rocketchip.system.DefaultConfig.behav_srams.v
     freechips.rocketchip.system.DefaultConfig.conf
     freechips.rocketchip.system.DefaultConfig.d
+    freechips.rocketchip.system.DefaultConfig.dts
     freechips.rocketchip.system.DefaultConfig.fir
+    freechips.rocketchip.system.DefaultConfig.graphml
+    freechips.rocketchip.system.DefaultConfig.json
+    freechips.rocketchip.system.DefaultConfig.memmap.json
+    freechips.rocketchip.system.DefaultConfig.plusArgs
+    freechips.rocketchip.system.DefaultConfig.rom.conf
     freechips.rocketchip.system.DefaultConfig.v
+    TestHarness.anno.json
     $ cat $ROCKETCHIP/vsim/generated-src/*.conf
     name data_arrays_0_ext depth 512 width 256 ports mrw mask_gran 8
     name tag_array_ext depth 64 width 88 ports mrw mask_gran 22
@@ -395,26 +416,26 @@ tests and benchmarks.
 ## <a name="param"></a> How can I parameterize my Rocket chip?
 
 By now, you probably figured out that all generated files have a configuration
-name attached, e.g. DefaultConfig. Take a look at
-src/main/scala/system/Configs.scala. Search for NSets and NWays defined in
-BaseConfig. You can change those numbers to get a Rocket core with different
+name attached, e.g. `freechips.rocketchip.system.DefaultConfig`. Take a look at
+`src/main/scala/system/Configs.scala`. Search for `NSets` and `NWays` defined in
+`BaseConfig`. You can change those numbers to get a Rocket core with different
 cache parameters. For example, by changing L1I, NWays to 4, you will get
 a 32KB 4-way set-associative L1 instruction cache rather than a 16KB 2-way
 set-associative L1 instruction cache.
-Towards the end, you can also find that DefaultSmallConfig inherits all
-parameters from BaseConfig but overrides the same parameters of
-WithNSmallCores.
+Towards the end, you can also find that `DefaultSmallConfig` inherits all
+parameters from `BaseConfig` but overrides the same parameters of
+`WithNSmallCores`.
 
-Now take a look at vsim/Makefile. Search for the CONFIG variable.
-By default, it is set to DefaultConfig.  You can also change the
+Now take a look at `vsim/Makefile`. Search for the `CONFIG` variable.
+By default, it is set to `freechips.rocketchip.system.DefaultConfig`.  You can also change the
 CONFIG variable on the make command line:
 
     $ cd $ROCKETCHIP/vsim
-    $ make -jN CONFIG=DefaultSmallConfig run-asm-tests
+    $ make -jN CONFIG=freechips.rocketchip.system.DefaultSmallConfig run-asm-tests
 
 Or, even by defining CONFIG as an environment variable:
 
-    $ export CONFIG=DefaultSmallConfig
+    $ export CONFIG=freechips.rocketchip.system.DefaultSmallConfig
     $ make -jN run-asm-tests
 
 This parameterization is one of the many strengths of processor
@@ -431,7 +452,7 @@ you can create your own Configuration(s) and compose them with Config's ++ opera
     }
     class MyConfig extends Config (new WithNExtInterrupts(16) ++ new DefaultSmallConfig)
 
-Then you can build as usual with CONFIG=MyConfig.
+Then you can build as usual with `CONFIG=<MyConfigPackage>.MyConfig`.
 
 ## <a name="debug"></a> Debugging with GDB
 
@@ -450,11 +471,11 @@ For that we need to add a Remote Bit-Bang client to the emulator. We can do so b
 To build the emulator with `DefaultConfigRBB` configuration we use the command:
 
     rocket-chip$ cd emulator
-    emulator$ CONFIG=DefaultConfigRBB make
+    emulator$ CONFIG=freechips.rocketchip.system.DefaultConfigRBB make
 
 We can also build a debug version capable of generating VCD waveforms using the command:
 
-    emulator$ CONFIG=DefaultConfigRBB make debug
+    emulator$ CONFIG=freechips.rocketchip.system.DefaultConfigRBB make debug
 
 By default the emulator is generated under the name `emulator-freechips.rocketchip.system-DefaultConfigRBB` in the first case and `emulator-freechips.rocketchip.system-DefaultConfigRBB-debug` in the second.