fix for chipsalliance/rocket-chip#2925

chipsalliance · Jun 5, 2022 · 13991a9 · 13991a9
1 parent 58bf5b3
commit 13991a9
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/ip/microsemi/polarfire_pcie_rootport/PolarFirePCIeRootPort.scala b/src/main/scala/ip/microsemi/polarfire_pcie_rootport/PolarFirePCIeRootPort.scala
@@ -330,7 +330,7 @@ class PolarFirePCIeX4(implicit p:Parameters) extends LazyModule
 
     //m
     m.aw.bits.cache := UInt(0)
-    m.aw.bits.prot  := AXI4Parameters.PROT_PRIVILEDGED
+    m.aw.bits.prot  := AXI4Parameters.PROT_PRIVILEGED
     m.aw.bits.qos   := UInt(0)
 
     m.aw.bits.id                        := blackbox.io.PCIESS_AXI_1_M_AWID
@@ -354,7 +354,7 @@ class PolarFirePCIeX4(implicit p:Parameters) extends LazyModule
     m.b.ready                           := blackbox.io.PCIESS_AXI_1_M_BREADY
 
     m.ar.bits.cache := UInt(0)
-    m.ar.bits.prot  := AXI4Parameters.PROT_PRIVILEDGED
+    m.ar.bits.prot  := AXI4Parameters.PROT_PRIVILEGED
     m.ar.bits.qos   := UInt(0)
 
     m.ar.bits.id                        := blackbox.io.PCIESS_AXI_1_M_ARID