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Make submodule inputs void in ExpandWhens #706

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merged 2 commits into from
Dec 20, 2017

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jackkoenig
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Fixes #705

The ports of submodules were not voided in ExpandWhens which means it does not error if they are not properly initialized. Worse still, since they don't have a default value in the netlist, the logic in ExpandWhens just picks the first connection and ignores all the rest.

I've added a test for each of the above cases.

@jackkoenig jackkoenig added this to the 1.0.1 milestone Dec 19, 2017
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Aside from the one comment/question this looks good to me.

case w: DefWire =>
netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid))
w
case w: DefMemory =>
netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), MALE) map (ref => we(ref) -> WVoid))
w
case w: WDefInstance =>
netlist ++= (getFemaleRefs(w.name, w.tpe, MALE).map(ref => we(ref) -> WVoid))
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MALE of getFemaleRefs here means to get all the inputs to the submodule?

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Clarified offline

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That's correct, similar to how it's used on the DefMemory above.

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Due to chipsalliance/chisel#746 this currently doesn't work with rocket-chip, I am trying to get this fixed tonight

@jackkoenig jackkoenig merged commit 4801d9c into master Dec 20, 2017
jackkoenig added a commit that referenced this pull request Dec 20, 2017
This is a modification of
#706 to preserve the
bugfix but preserve the [buggy] API that firrtl was not properly
enforcing initialization requirements for submodule inputs
jackkoenig added a commit that referenced this pull request Dec 20, 2017
This is a modified form of
#706 to preserve the
bugfix but preserve the [buggy] 1.0.x API that firrtl was not properly
enforcing initialization requirements for submodule inputs
jackkoenig added a commit that referenced this pull request Dec 21, 2017
This is a modified form of
#706 to preserve the
bugfix but preserve the [buggy] 1.0.x API that firrtl was not properly
enforcing initialization requirements for submodule inputs. If a
submodule port is not properly invalidated, ExpandWhens will print a
warning.
ucbjrl added a commit that referenced this pull request Dec 21, 2017
ucbjrl added a commit that referenced this pull request Dec 21, 2017
…as 712)

This is a modified form of #706 to preserve the
bugfix but preserve the [buggy] 1.0.x API that firrtl was not properly
enforcing initialization requirements for submodule inputs

The problem with #706 is that because Firrtl wasn't properly enforcing initialization requirements on submodules, code that used to work no longer does. This alternative version still fixes the incorrect Verilog generation bug but does not enforce the initialization requirement.
@jackkoenig jackkoenig deleted the fix-submodule-invalidate branch January 23, 2019 04:43
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3 participants