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latest FIRRTL generates incorrect code in rocket-chip #705
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(also, how come I didn't get the fancy template for filing my issue? How is that flow supposed to work)? |
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Because I forgot to approve and merge #699. Anyway I've narrowed down the bug, fix coming soon. For those interested, if you don't invalidate input ports of a submodule and yet you only connect to them conditionally, it drops most of the conditional connections and picks one (I think the last one). This hasn't come up because Chisel was invalidating everything by default, but with the invalidate API, it doesn't anymore. |
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Fixes #746 Also add test for chipsalliance/firrtl#705
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Fixes #746 Also add test for chipsalliance/firrtl#705
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…#747) Fixes #746 Also add test for chipsalliance/firrtl#705
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See chipsalliance/rocket-chip#1160
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