Submodule ports not properly invalidating in compatibility code

[jackkoenig]

Instantiating an Arbiter (and possibly chisel3 modules in general) inside of compatibility code can lead to the ports of the submodule not being properly invalidated.

• Type of issue

  • Bug report
  • Feature request
  • Other enhancement

• If the current behavior is a bug, please provide the steps to reproduce the problem:

  • What is the current behavior?
  • What is the expected behavior?
  • Please tell us about your environment:
    (examples)
    • version: 3.0-SNAPSHOT
    • OS: Linux knight 4.4.0-92-generic #115-Ubuntu SMP Thu Aug 10 09:04:33 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux

Consider:

import Chisel._

class InvalidateBugTop extends Module {
  val io = IO(new Bundle {
    val in = Vec(2, Decoupled(UInt(32.W)).flip())
    val out = Decoupled(UInt(32.W))
  })
  val arb = Module(new Arbiter(UInt(32.W), 2))
  arb.io.in <> io.in
  io.out <> arb.io.out
}


object InvalidateBugDriver extends App {
  chisel3.Driver.execute(args, () => new InvalidateBugTop)
}

The resulting Firrtl does not have an invalidate on the io of the Arbiter:

  module InvalidateBugTop :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}

    clock is invalid
    reset is invalid
    io is invalid
    inst arb of Arbiter @[InvalidateBug.scala 9:19]
    arb.clock <= clock
    arb.reset <= reset
    arb.io.in <- io.in @[InvalidateBug.scala 10:13]
    io.out <- arb.io.out @[InvalidateBug.scala 11:10]

Combined with chipsalliance/firrtl#706, this can emit incorrect Verilog (working on an example)

• What is the use case for changing the behavior?

Fix expected behavior in compatibility mode

• Impact

  • no functional change
  • API addition (no impact on existing code)
  • API modification
  • unknown

• Development Phase

  • request
  • proposal

• Other information (e.g. detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, eg. Stack Overflow, gitter, etc)

Strangely, I tried making a similar example with a Queue as the submodule instead of an Arbiter, but it correctly invalidated the Queue's io.

[jackkoenig]

While this is a weird thing to write, the following will currently generate incorrect Verilog (because of this bug combined with the bug in Firrtl). If you explicitly connect arb.io to chisel3.DontCare, it will do the right thing, but these ports should be invalidated automatically in Chisel._ code!

import Chisel._

class InvalidateBugTop extends Module {
  val io = IO(new Bundle {
    val in = Vec(2, Decoupled(UInt(32.W)).flip())
    val altIn = Decoupled(UInt(32.W)).flip()
    val out = Decoupled(UInt(32.W))
  })
  val arb = Module(new Arbiter(UInt(32.W), 2))
  arb.io.in(1) <> io.in(1)

  io.altIn.ready := arb.io.in(0).ready
  io.in(0).ready := arb.io.in(0).ready

  when (io.altIn.valid) {
    arb.io.in(0).bits := io.altIn.bits
    arb.io.in(0).valid := true.B
  } .otherwise {
    arb.io.in(0).bits := io.in(0).bits
    arb.io.in(0).valid := io.in(0).valid
  }
  io.out <> arb.io.out
}