Merge pull request sysprog21#108 from Risheng1128/riscof

Migrate to RISC-V Compatibility Framework (RISCOF)

.ci/riscv-tests.sh

@@ -7,20 +7,23 @@ check_platform
 mkdir -p toolchain
 
 # GNU Toolchain for RISC-V
-GCC_VER=12.2.0-1
-XPACK_REPO=https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download
+GCC_VER=2023.01.04
+TOOLCHAIN_REPO=https://github.com/riscv-collab/riscv-gnu-toolchain/releases
+
+# Install RISCOF
+python3 -m pip install git+https://github.com/riscv/riscof
 
 set -x
 
 wget -q \
-    ${XPACK_REPO}/v${GCC_VER}/xpack-riscv-none-elf-gcc-${GCC_VER}-linux-x64.tar.gz -O- \
+    ${TOOLCHAIN_REPO}/download/${GCC_VER}/riscv32-elf-ubuntu-22.04-nightly-${GCC_VER}-nightly.tar.gz -O- \
 | tar -C toolchain -xz
 
-export PATH=`pwd`/toolchain/xpack-riscv-none-elf-gcc-${GCC_VER}/bin:$PATH
+export PATH=`pwd`/toolchain/riscv/bin:$PATH
 
 make clean
 make arch-test RISCV_DEVICE=I || exit 1
-make arch-test RISCV_DEVICE=M  || exit 1
-make arch-test RISCV_DEVICE=C || exit 1
-make arch-test RISCV_DEVICE=Zifencei || exit 1
-make arch-test RISCV_DEVICE=privilege || exit 1
+make arch-test RISCV_DEVICE=IM  || exit 1
+make arch-test RISCV_DEVICE=IC || exit 1
+make arch-test RISCV_DEVICE=IZifencei || exit 1
+make arch-test RISCV_DEVICE=IZicsr || exit 1

.gitignore

@@ -13,3 +13,5 @@ build/mini-gdbstub
 *.o
 *.o.d
 tests/**/*.elf
+tests/arch-test-target/config.ini
+__pycache__/

mk/riscv-arch-test.mk

@@ -1,18 +1,15 @@
 ARCH_TEST_DIR ?= tests/riscv-arch-test
-ARCH_TEST_BUILD := $(ARCH_TEST_DIR)/Makefile
 export RISCV_TARGET := tests/arch-test-target
-export RISCV_PREFIX ?= $(CROSS_COMPILE)
 export TARGETDIR := $(shell pwd)
-export XLEN := 32
-export JOBS ?= -j
 export WORK := $(TARGETDIR)/build/arch-test
+export RISCV_DEVICE ?= IMCZicsrZifencei
 
-$(ARCH_TEST_BUILD):
-	git submodule update --init $(dir $@)
+arch-test: $(BIN)
+	git submodule update --init $(dir $(ARCH_TEST_DIR))
 
-arch-test: $(BIN) $(ARCH_TEST_BUILD)
-ifndef CROSS_COMPILE
-	$(error GNU Toolchain for RISC-V is required. Please check package installation)
-endif
-	$(Q)$(MAKE) --quiet -C $(ARCH_TEST_DIR) clean
-	$(Q)$(MAKE) --quiet -C $(ARCH_TEST_DIR)
+	$(Q)python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE)
+
+	$(Q)riscof run --work-dir=$(WORK) \
+			--config=$(RISCV_TARGET)/config.ini \
+			--suite=$(ARCH_TEST_DIR)/riscv-test-suite \
+	   		--env=$(ARCH_TEST_DIR)/riscv-test-suite/env

tests/arch-test-target/constants.py

@@ -0,0 +1,29 @@
+import os
+
+dutname = 'rv32emu'
+refname = 'sail_cSim'
+
+root = os.path.abspath(os.path.dirname(__file__))
+cwd = os.getcwd()
+
+misa_C = (1 << 2)
+misa_F = (1 << 5)
+misa_M = (1 << 12)
+
+config_temp = '''[RISCOF]
+ReferencePlugin={0}
+ReferencePluginPath={1}
+DUTPlugin={2}
+DUTPluginPath={3}
+
+[{2}]
+pluginpath={3}
+ispec={3}/{2}_isa.yaml
+pspec={3}/{2}_platform.yaml
+path={4}/build
+target_run=1
+
+[{0}]
+pluginpath={1}
+path={1}
+'''

tests/arch-test-target/link.ld → tests/arch-test-target/rv32emu/env/link.ld

@@ -12,4 +12,4 @@ SECTIONS
   .data.string : { *(.data.string)}
   .bss : { *(.bss) }
   _end = .;
-}
+}

tests/arch-test-target/rv32emu/env/model_test.h

@@ -0,0 +1,50 @@
+#pragma once
+
+/* clang-format off */
+#define RVMODEL_DATA_SECTION                          \
+    .pushsection .tohost,"aw",@progbits;              \
+    .align 8; .global tohost; tohost: .dword 0;       \
+    .align 8; .global fromhost; fromhost: .dword 0;   \
+    .popsection;                                      \
+    .align 8; .global begin_regstate; begin_regstate: \
+    .word 128;                                        \
+    .align 8; .global end_regstate; end_regstate:     \
+    .word 4;
+/* clang-format on */
+
+// RV_COMPLIANCE_HALT
+#define RVMODEL_HALT \
+    add a7, x0, 93;  \
+    add a0, x0, 0;   \
+    ecall
+
+#define RVMODEL_BOOT
+
+// RV_COMPLIANCE_DATA_BEGIN
+#define RVMODEL_DATA_BEGIN        \
+    RVMODEL_DATA_SECTION.align 4; \
+    .global begin_signature;      \
+    begin_signature:
+
+// RV_COMPLIANCE_DATA_END
+#define RVMODEL_DATA_END   \
+    .align 4;              \
+    .global end_signature; \
+    end_signature:
+
+// RVTEST_IO_INIT
+#define RVMODEL_IO_INIT
+// RVTEST_IO_WRITE_STR
+#define RVMODEL_IO_WRITE_STR(_R, _STR)
+// RVTEST_IO_CHECK
+#define RVMODEL_IO_CHECK()
+// RVTEST_IO_ASSERT_GPR_EQ
+#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
+// RVTEST_IO_ASSERT_SFPR_EQ
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+// RVTEST_IO_ASSERT_DFPR_EQ
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+#define RVMODEL_SET_MSW_INT
+#define RVMODEL_CLEAR_MSW_INT
+#define RVMODEL_CLEAR_MTIMER_INT
+#define RVMODEL_CLEAR_MEXT_INT