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Migrate to RISC-V Compatibility Framework (RISCOF) #108

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merged 1 commit into from
Feb 6, 2023

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Risheng1128
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This commit updates the version of riscv-arch-test and introduces the RISC-V Architectural Test Framework (RISCOF) into emulator.

In riscv-arch-test part, the following shows the old and revised version.

  • Old: branch old-framework-2.x
  • New: branch main and commit 933dddd

In RISCOF part, it uses config.ini to configure the plugins to be used — the device-under-test (DUT) and the reference model (REF). The ISA specification defines the available ISA extensions in emulator and users can modify via YAML file in DUT's folder. The file setup.py generates the config.ini automatically and modifies the ISA specification based on user's input.

  • DUT: rv32emu
  • REF: sail_cSim

endif
$(Q)$(MAKE) --quiet -C $(ARCH_TEST_DIR) clean
$(Q)$(MAKE) --quiet -C $(ARCH_TEST_DIR)
$(Q) python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE)
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There is no space between $(Q) and python3. That is, $(Q)python3.

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Append "Close #49" at the end of git commit message. In addition, summarize the test report based on the latest revision of rv32emu.

This commit updates the version of riscv-arch-test and introduces the
RISC-V Architectural Test Framework (RISCOF) into emulator.

In riscv-arch-test part, the following shows the old and revised version.
- Old: branch old-framework-2.x
- New: branch main and commit 933dddd

In RISCOF part, it uses config.ini to configure the plugins to be used —
the device-under-test (DUT) and the reference model (REF). The ISA
specification defines the available ISA extensions in emulator and users
can modify via YAML file in DUT's folder. Besides, the file setup.py generates
 the config.ini automatically and modifies the ISA specification based on user's
input.
- DUT: rv32emu
- REF: sail_cSim

In the other hand, RISCOF uses riscv-gnu-toolchain to compile the tests in
riscv-arch-test. Therefore, change the toolchain from riscv-none-elf-gcc-xpack
to riscv-gnu-toolchain in Continuous Integration (CI).

Finally, summarize the test report based on the latest revision of rv32emu.
- Passed ISA in riscv-arch-test: I, M, C, Zicsr (privilege), Zifencei

Close sysprog21#49
@jserv jserv merged commit eaeb49f into sysprog21:master Feb 6, 2023
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jserv commented Feb 6, 2023

Thank @Risheng1128 for the great work!

@Risheng1128 Risheng1128 deleted the riscof branch February 6, 2023 18:39
vestata pushed a commit to vestata/rv32emu that referenced this pull request Jan 24, 2025
Migrate to RISC-V Compatibility Framework (RISCOF)
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2 participants