UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
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Updated
Jun 24, 2025 - SystemVerilog
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yapp
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A complete UVM-based verification environment for validating YAPP Router functionality using SystemVerilog and Cadence Xcelium, featuring advanced sequences, virtual interfaces, and coverage analysis.
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Updated
Jun 27, 2025 - SystemVerilog
UVM testbench demonstrating multi-UVC integration for YAPP router verification with HBUS register interface, channel protocol monitoring, and comprehensive SystemVerilog verification methodologies.
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Updated
Jun 29, 2025 - SystemVerilog
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