IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.

Innervator: Hardware Acceleration for Neural Networks

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela

A pedagogical processor on FPGA, developed at NIIT University.

Design of an arithmetic logic (ALU). It typically performs mathematical and logical functions. An ALU is designed and implemented using VHDL.

Verilog code practice using the Xilinx Vivado design suite

Codes for VHDL programming for VLSI designing.

Fast VHDL language server written in Rust

Mi Proyecto Integrador para obtener el título de Ingeniero Electrónico. Course completion assignment for Electronic Engineer Degree.