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verilog-hdl

Here are 42 public repositories matching this topic...

mirseo / JSilicon

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core

Updated Oct 9, 2025
SystemVerilog

Weiyet / RTLStructLib

RTL data structure

data-structures rtl system-verilog verilog-hdl cocotb uvm-verification

Updated Aug 10, 2025
SystemVerilog

mohasnik / Network-On-Chip

RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.

verilog systemverilog verilog-hdl system-design network-on-chip rtl-tests rtl-de

Updated Jul 12, 2024
SystemVerilog

semahawk / wishbone

Trying to learn Wishbone by implementing few master/slave devices

verilog verilog-hdl wishbone wishbone-bus

Updated Jan 7, 2019
SystemVerilog

LSC-Unicamp / processor_ci

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

hardware eda ci-cd riscv verilog cicd verilog-hdl risc-v

Updated Oct 9, 2025
SystemVerilog

williaml33moore / bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Nov 16, 2024
SystemVerilog

VLSI-Design-Verification-Projects

SACHINUR17 / VLSI-Design-Verification-Projects

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Updated Sep 13, 2025
SystemVerilog

BrianHGinc / BHG_I2C_init_RS232_debugger

A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.

i2c verilog rs232 verilog-hdl

Updated Jun 26, 2023
SystemVerilog

xver / icecream_sv

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

debugging debug systemverilog verilog-hdl icecream debugging-tools systemverilog-hdl systemverilog-simulation systemverilog-developer systemverilog-test-bench

Updated Aug 29, 2025
SystemVerilog

yuri-panchul / tt08-adder-with-flow-control

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

verilog systemverilog verilog-hdl microarchitecture systemverilog-hdl verilog-project verilog-code

Updated Sep 5, 2024
SystemVerilog

Shuregg / riscv-simple-cpu

Creating a risc-v processor

cpu verification riscv rtl verilog systemverilog verilog-hdl risc-v riscv32

Updated Apr 4, 2024
SystemVerilog

imjp2020 / UVM_FIFO_TB

This testbench is based on SV and UVM Class based to verify Verilog HDL Design

uvm system-verilog verilog-hdl

Updated Mar 23, 2023
SystemVerilog

kl10

alanmimms / kl10

KL10PV (also called "model B") CPU implemented in SystemVerilog for Xilinx FPGA from MP00301_KL10PV_Jun80 PDFs trying to remain faithful to the original while I learn Verilog

fpga systemverilog pdp-10 verilog-hdl systemverilog-hdl mainframe-emulator

Updated Jun 12, 2020
SystemVerilog

kyori19 / verilog-otp

VerilogHDL implementation of One-Time Password Algorithm (HOTP)

hotp verilog systemverilog verilog-hdl onetimepassword

Updated Oct 29, 2022
SystemVerilog

prithvi-narayan-bhat / Custom_RISC_Implementation

An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set

linux arm assembly intel riscv verilog hdl verilog-hdl risc-v quartus-prime systemverilog-hdl riscv32

Updated May 13, 2023
SystemVerilog

SvrAdityaReddy / Inter_Device_Communication_Protocols

Verilog Codes of various Inter Device Communication Protocols

verilog-hdl systemverilog-hdl

Updated Apr 28, 2018
SystemVerilog

Mips-MultiCycle

kalhorghazal / Mips-MultiCycle

Mips Multi-Cycle, Computer Architecture course, University of Tehran

mips verilog-hdl mips-architecture mips-processor multi-cycle-processor

Updated Aug 4, 2020
SystemVerilog

ankangd / 4bitPC

Verilog-HDL implementation of a simple 4-bit PC.

verilog-hdl verilog-project 4-bit-cpu

Updated Apr 17, 2021
SystemVerilog

Soham-coder / ROCC_based_neurosynapse

ROCC accelerator ISA based neuroSynapse

testing fsm state-machine random systemverilog verilog-hdl rocc rocketchip-rocc

Updated Nov 3, 2021
SystemVerilog

SKpro-glitch / Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level

Updated Jun 19, 2025
SystemVerilog

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