General Purpose I/O agent written in UVM
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Updated
Jun 29, 2017 - SystemVerilog
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uvc
Here are 4 public repositories matching this topic...
UVM VIP for Single Port RAM Synchronous Read/Write
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Jul 15, 2020 - SystemVerilog
Python script to create sequence item from spreadsheet
python network ip verilog systemverilog canbus uvm testbench uvc uart-protocol protocol-oriented-programming canbus-communications canbus-communication
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Apr 24, 2025 - SystemVerilog
UVM testbench demonstrating multi-UVC integration for YAPP router verification with HBUS register interface, channel protocol monitoring, and comprehensive SystemVerilog verification methodologies.
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Updated
Jun 29, 2025 - SystemVerilog
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