VLSI System Design Practice Lab
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Apr 21, 2020 - Verilog
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test-bench
Here are 4 public repositories matching this topic...
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
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Aug 24, 2024 - Verilog
This is an implementation of a MIPS for the computer architecture subject.
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Jan 26, 2025 - Verilog
Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
fpga verilog computer-architecture test-bench mips-processor digital-design computer-organization combinational-logic sequential-logic
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Jul 5, 2024 - Verilog
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