An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。
-
Updated
Sep 14, 2023 - Verilog
#
rmii
Here are 2 public repositories matching this topic...
verilog modules
synchronization fpga i2c memory timer verilog spi xilinx uart usart 7-segment xilinx-fpga nexys4 pll rmii nexys-4-spartan-3e nexys4-board
-
Updated
May 4, 2020 - Verilog
Improve this page
Add a description, image, and links to the rmii topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the rmii topic, visit your repo's landing page and select "manage topics."