8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

A collection of phase locked loop (PLL) related projects

Arduino Si5351 library tuned for size and click free.

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

sensorless fixed point foc use smo and pll in stm32

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

RFFC2071 C8051F330

FOC driver library written in Rust

verilog modules

This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.

Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

<Pll/> React Programming Language Logo Component.

Support files for blog posts of Zurich Instruments

All Digital Phase-Locked Loop

Sensorless FOC (PLL estimator) of AC induction motor with field weakening