Matrix multiplication on multiple Nios II cores

A toy L4 load balancer running on FPGA

Zalt is a home brew Z80 computer with a modern(isch) chipset.

Use an MPSSE FTDI device as a JTAG interface in Quartus tools

SHA3-256 MINER CORE

EDA Tools: Altera Quartus 13 Dockerfile

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...

FPGA and RTOS based video display driver for an LED matrix, with HTTP control over WiFi

A small utility to reverse bit order of the output bitstream generated by Quartus ii before it can be flashed into the FPGA flash memory of the arduino vidor MK4000.

System for Cyclone IV FPGA dev board that consist of RISC-V CPU, custom OS, DMA, controllers and drivers for peripherals.

Bizzas CPU design

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Collection of all projects done up to date in Computer Science and Engineering at the UC3M

Senior Capstone Project

This project maps the behavior between input buttons and output LEDs using Quartus II 13.0sp platform alongside with Qsys. Moreover, a C source file to control the components created beforehand.