DPU on PYNQ

PYNQ Composabe Overlays

Networking Overlay on PYNQ

IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors

PYNQ with Chisel and Rust

Userspace DMA library for Zynq-based SoCs

Demonstration of Automatic Gain Control with PYNQ

PYNQ DMA benchmark project

IP core with AXI interface for reading the Device DNA from the PL of Zynq 7000 devices

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

Design of High-Level Synthesis of Xilinx FFT IP core via FFT library

PYNQ board spec files for Alinx ZYNQ UltraScale FPGA boards

HARDWARE API (HAPI): PYNQ HARDWARE OVERLAY WITH DES ACCELERATOR

PYNQ for Zybo board

C4.5 decision tree overlay for machine learning algorithms on PYNQ

This is a design for the test of AXI_HP on PYNQ-Z1 (as well as Z2, maybe)

PYNQ Festival

A few adder examples based on various AXI interfaces

PYNQ enabled Genesys ZU Open Source Instrument, based on Pavel Demin's Red Pitaya Notes workflow.

PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx