Verilog Implementation of an ARM LEGv8 CPU
LEGv8 CPU implementation and some tools like a LEGv8 assembler
Super scalar Processor design
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
The final project of computer architecture and it is a 5-stage mips CPU implemented by Verilog.
The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
Verilog implementation of pipelined MIPS processor
Unconventional MIPS Architecture CPU with Pipeline structure with fewer stalls and advanced units to ensure smallest possible CPI. Designed in Verilog and contains simulation and implementation for Xilinx Basys 3 board
Verilog Implementation of an ARM LEGv8 CPU
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