This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
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Jul 19, 2022 - Verilog
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openlane-flow
Here are 6 public repositories matching this topic...
The SAP-1 in Verilog, and now as an ASIC!
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Nov 5, 2022 - Verilog
This is part of EC383 - Mini Project in VLSI Design.
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May 8, 2022 - Verilog
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
open-source processor-architecture asic fpga verilog hardware-designs vlsi verilog-hdl risc-v riscv32 asic-verification processor-design vlsi-design asic-design openlane openlane-flow
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Jan 10, 2025 - Verilog
VSDMemSOC Implementation flow:: RTL2GDSII
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Mar 1, 2024 - Verilog
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
opensource verification synthesis gds cts netlist placement klayout floorplan openlane openlane-flow openlane-github- netlist-simulation-
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Mar 8, 2024 - Verilog
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