RISCV-Processor-ASIC

Author: Soham Kapur
Description: This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

Name		Name	Last commit message	Last commit date
Latest commit History 62 Commits
ALU.v		ALU.v
Branch.v		Branch.v
Decode.v		Decode.v
Execute.v		Execute.v
Fetch.v		Fetch.v
Loadstore.v		Loadstore.v
Processor.v		Processor.v
Processor_Compiled.v		Processor_Compiled.v
Prog_Count.v		Prog_Count.v
Prog_Mem.v		Prog_Mem.v
RAM.v		RAM.v
README.md		README.md
RISC-V_Sync_BlockDiagram.png		RISC-V_Sync_BlockDiagram.png
Synchronous_Core.v		Synchronous_Core.v

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