CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Single-Cycle RISC-V Processor in systemverylog

study uvm step by step

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

simple read/write pcap tasks for SystemVerilog test

CAPIPrecis a Coherent Accelerator Processor Interface (CAPI) Abstract Layer

Pipeline Processor based on RISC-V, implemented forwarding and hazard detection units

The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA

test task from company

Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL

This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques

Scrolling Display Implemented With Digital Design Concepts on De1-SoC

UART Receiver and Transmitter using Terasic DE-10 Standard FPGA

Simple register realisation for SystemVerilog Verification

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

Computer Architecture Lab - Assignments - Fall 2023