SystemVerilog examples for a digital design course
-
Updated
Mar 30, 2021 - SystemVerilog
#
logic-design
Here are 5 public repositories matching this topic...
A collection of digital logic circuits
-
Updated
Sep 24, 2020 - SystemVerilog
An implementation of the MaxNet network in Verilog, designed as a TA for the CAD course at the University of Tehran (Fall 2023)
-
Updated
Nov 1, 2024 - SystemVerilog
Design of mips pipeline microprocessor architecture using system verilog
-
Updated
Jun 21, 2017 - SystemVerilog
Created a state machine for a sequential circuit game called "Stop It," which is programmed onto a Basys 3 FPGA Board. The project emphasizes understanding state machines, sequential circuits, and FPGA.
-
Updated
Aug 14, 2024 - SystemVerilog
Improve this page
Add a description, image, and links to the logic-design topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the logic-design topic, visit your repo's landing page and select "manage topics."