An FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。

DisplayPort IP-core

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.

Microarquitecturas y Softcores - CESE - FIUBA

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.