a project to check the FOSS synthesizers against vendors EDA tools
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Updated
Sep 26, 2020 - Makefile
a project to check the FOSS synthesizers against vendors EDA tools
HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, and the plugins ghdl-yosys-plugin and yosys-slang.
VHDL examples targeting the ICE40-HX8K development board using iceStorm + GHDL
Docker image for fpga development
Containers for FOSS tools
A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project
Some examples using VHDL in combination with the icebreaker board
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