Must-have verilog systemverilog modules

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Asynchronous FIFO for transferring data between two asynchronous clock domains

FIFO implementation with different clock domains for read and write.

RTL of a parametrized asynchronous FIFO that allows for variable depth, data width, and includes almost empty/full flags.

A coocbook of HDL (primarily Verilog) modules

Collection of utility modules written in Verilog

All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

华中科技大学网络空间安全学院密码工程学基础2023(密码硬件工程)

Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

codes of my IUT FPGA LAB

A project to implement and test synchronous and asynchronous FIFO using Questasim software.

Eight different verilog projects are combined to creat a big custom asic project.

This Repository was created and aimed to study FIFO vs FWFT.

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

Verilog Mini Projects

Verilog implementation of UART protocol with integrated FIFO buffer

Digital System Design Verilog Implementation

Simple UART RX that fills a FIFO queue. Pop the FIFO to LEDs by pressing the button