std_module

---

A simplified one stop RTL library for all the basic Verilog modules.

Contents ( List of modules )

• Basic Gates
  • AND
  • OR
  • NOT
  • NOR
  • NAND
  • XOR
  • XNOR
• Logic Modules
  • Multiplexer 2x1
  • Multiplexer Nx1 ( Module Script )
  • DeMultiplexer 1x2
  • DeMultiplexer 1xN ( Module Script )
  • Encoder NxM
  • Decoder MxN
• Arithematic Modules
  • Half Adder
  • Full Adder
  • Half Subtractor
  • Full Subtractor
• Sequential Modules
  • Left Shifter ( SISO )
  • Right Shifter ( SISO )
  • Left-Right Shifter ( SISO )
  • Parallel Load Cyclic Left Serial Shifter ( PISO )
• Buffer Modules
  • Synchronous FIFO
    • Synchronous FIFO ( v1 ) [ Ongoing Lint Issues ]
  • Asynchronous FIFO
    • Asynchronous FIFO ( v1 )

Note :

All the modules here are designed in the behavioural format of the RTL code. It is quiet unlikely that you will find any hardcore structural code in here. If there are any, I'll make sure to mention it in this list here, so its easier to keep track of. Some modules, such as the FIFOs have a few variations in them with respect to the specification used. In that case, you can either use the design doc as reference ( which may be avialable in the directory itself ) or you can look at the description of the module provided in the comments of the module's source file.