A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.

A simple direct-mapped cache modeled by Verilog. Part of Spring 2019 Computer Architecture course at the University of Tehran.

The repository simulates direct-mapped and four way set associative cahe.

CPP Program to simulate a Generalized Cache behaviour

Dual hierarchy (L1 and L2) cache simulator with direct mapping and two way associative configurations. Project for Computer Organization class.

My Solutions to Computer Architecture Course Practical Assignments

A simple implementation of a Direct Mapped Cache and Set Associative Cache in C++. Supports for different sizes of the cache, block, #ways, etc.

Low-level programming assignments, "Low-Level Programming" (TDT4258) course, fall 2023.