This project is a Computer Architecture Design and Data Path Simulator which simulates a modified MIPS datapath with pipelining written in Java.

Repository regarding the Practical Works of the Computer Organization discipline

EE89H Final Project

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

Implements a datapath which is capable of executing a subset of the Motorola HC08 instruction set on a Field Programmable Gate Array (FPGA).

In a Single Cycle Datapath, each of the Datapath's components carries out an instruction in one cycle. Therefore, no Datapath component may be utilized more than once each cycle.

VHDL module for histogram equalization, aiming to enhance image contrast using digital circuit design techniques in VHDL

Made a fully functional CPU model capable of performing essential computing tasks, such as executing instructions from memory, handling data with load and store operations.

🕹️ Mastermind game written in VHDL

Simple 16-bit CPU written in Verilog.

Simple software for the monitoring of heartbeats.

some mini-projects, developed in my digital system's class, based on: combinational/sequential logic design, hardware description languages (VHDL), datapath components, register-transfer level (RTL) design and introduction to programmable processors, with a physical implementation in SSI IC's, ASIC's, FPGA's, PLD's.

An implementation of Mips processor - My Computer Architecture course final project

FIFO and DMA combination study - "CY8C5888AXI-LP096" on "FreeSoC2"

Código Verilog da implementação do TP2 de OC1

Design in VHDL of an hardware component for the Logic Circuit Design course @ PoliMi

4 staged MIPS verilog processor

Learned as a part of Computer architecture Course