PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities

A universal mechanism for implementing Functional Mock-up Units (FMUs) in various languages

Virtual development board for HDL design

Virtio front-end and back-end bridge, implemented with FPGA.

A platform for emulating Virtio devices with FPGAs

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m