Welcome Cybersecurity's World. An ongoing & curated collection of awesome software best practices and techniques, libraries and frameworks, E-books and videos, websites, blog posts, links to github Repositories, technical guidelines and important resources in Cybersecurity.

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…

Simulator + benchmark suite for Micro Aerial Vehicle design.

Explore a collection of resources and projects in Computer Science, covering algorithms, data structures, programming languages, and emerging technologies. Ideal for learners and enthusiasts looking to enhance their knowledge and skills in the field

SBTCVM is a virtual machine implementation of a balanced ternary (base 3) computer. Features several compiled languages for ternary software development.

Course files for ECS 154A in Winter Quarter 2020.

Accelerating Recommender model training by leveraging popular choices -- VLDB 2022

CS 211 Computer Architecture at Rutgers University

A 16-bit RISC-V Inspired ISA

These are the Python implementations of FIFO, LRU and OPT page replacement algorithms

Computer architecture project : Cache simulator with LRU replacement policy

A simple script to plot the Roofline model for given HW platforms and applications

Virtualização de uma CPU 8-bits, no logisim, com instruções Assembly em formato inspirado no MIPS-Assembly.

A Python program for simulating different kinds of computer caches

MegIS is the first in-storage processing system designed to significantly reduce the data movement overhead of the end-to-end metagenomic analysis pipeline. Described in the ISCA 2024 paper by Mansouri Ghiasi et al.: https://arxiv.org/pdf/2406.19113

Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.

LC-3 VM Python implementation.

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Simulates Tomasulo Algorithms with Reorder Buffer

Developing a MIPS Instruction Interpreter