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clock-domains

Here are 5 public repositories matching this topic...

hdl-util / clock-domain-crossing

Utilities for clock-domain crossing with an FPGA

fpga verilog systemverilog clock-synchronization clock-domain-crossing clock-domains

Updated Jun 27, 2020
SystemVerilog

w-tr / clock-domain-crossing

In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.

synchronization clock cdc clock-design clock-synchronization clock-domain-crossing clock-domains

Updated Nov 20, 2020
VHDL

zslwyuan / Zynq_HLS_DDR_AXI_IPs_Multiple_Clock

zynq hls dataflow vivado high-level-synthesis clock-domains

Updated Sep 7, 2019
VHDL

zslwyuan / Hi-ClockFlow

Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

hls dataflow vivado high-level-synthesis vivado-hls multi-clock-dataflow clock-domains hi-clockflow

Updated Apr 11, 2024

MarleyLobao / UVM-mult-clk-domain

Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.

hardware-verification clock-domains uvm-virtual-sequence

Updated Feb 29, 2024
SystemVerilog

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