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  1. AMF-Placer Public

    AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

    C++ 101 19

  2. Light-HLS Public

    Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

    C++ 60 21

  3. PAAS_V1.0 Public

    PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

    Ada 43 16

  4. Hi-DMM Public

    Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

    VHDL 25 10

  5. LLVM-9.0-Learner-Tutorial Public

    A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

    C++ 103 23

  6. Basic-SIMD-Processor-Verilog-Tutorial Public

    Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

    Verilog 129 34

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Contributed to zslwyuan/Hi-ClockFlow
Loading A graph representing zslwyuan's contributions from April 07, 2024 to April 07, 2025. The contributions are 100% commits, 0% issues, 0% pull requests, 0% code review.

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April 2025

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