Chisel: A Modern Hardware Design Language

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

educational microarchitectures for risc-v isa

Provides dot visualizations of chisel/firrtl circuits

Lectures for the Agile Hardware Design course in Jupyter Notebooks

100 Days of CHISEL inspired by 100DaysOfRTL

🌳 The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"

Yet another toy CPU.

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

An exquisite superscalar RV32GC processor.

Documentation for YatCPU

A caravan equipped with API for creating bus protocols in Chisel with ease.

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Quasar 2.0: Chisel equivalent of SweRV-EL2

Chisel library for Unum Type-III Posit Arithmetic

Chisel Things for OFDM

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.