Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
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Jan 24, 2021 - Verilog
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product
This repository consists of verilog codes for Digital VLSI Lab (EC39004), IIT KGP.
csd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.
⚡This project aims to implement 6 different multipliers including the radix-4 booth multiplier, a multiplier tree, floating-point multiplier and more.. in verilog as well as synthesize each one on Oasys with appropriate scripts and finally route the complete design on Nitro to obtain its layout. DRC and LVS checks were also made for floating-point.
designed simple digital circuits using verilog
Multiplicador de Booth de 2 bit con mejoras en la estructura
Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.
Projects of the computer architecture course (Fall01) at the University of Tehran.
Verilog Multiplier Implementation
Verilog implementation of the Booth's multiplication algorithm.
Contains implementation of Binary Multiplier in verilog
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