A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Embedded firmware for ham radio transceivers

Altera JTAG UART wrapper for Bluespec

Matrix Multiplication in Hardware

Zalt is a home brew Z80 computer with a modern(isch) chipset.

ZX BUS Kempston Mouse Controller

EDA Tools: Altera Quartus 13 Dockerfile

Altera USB-Blaster-compatible programmer on Raspberry Pi Pico

32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Altera wrappers for C applications using Altera's 16550 UART Core through Avalon Bus on Cyclone V.

This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA

This program is to assist as a toolset for OpenCl's FPGA SDK. Since the OpenCL has a certain standard and procedure of compiling and transferring mehods to the board, this tool set was written to assist in plain english.

Driver - Library for C applications using Altera's UART Core through Avalon Bus on Cyclone V.

The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example

Standalone JTAG virtual jtag driver/programmer for DE0-Nano/USB-Blaster

USB-Blaster firmware that runs on cheap with CH552G chip

Simple snake game written in C for the Altera DE0-CV FPGA