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altera-de1

Here are 13 public repositories matching this topic...

Bennyaw / SimpleProcessor_Verilog

A simple processor designed using Verilog and Altera DE1 development board.

simple modelsim verilog-hdl quartus processor-design altera-de1

Updated Apr 22, 2020
Verilog

pedro-javierf / AlteraDE1pinfiles

Pin file in .qsf format for Altera DE1 FPGA

fpga intel archive altera preservation fpa altera-de1 altera-de1-fpga qsf-format pin-file

Updated Dec 18, 2023
Tcl

chkrr00k / sram-controller

A simple sram controller and test for the altera DE1 FPGA board

vhdl sram vhdl-modules altera-fpga vhdl-coursework sram-controller vhdl-sram altera-de1 terasic-de1

Updated Apr 2, 2019
VHDL

ismailfaruk / ECSE324--Computer-Organization

Academic projects created using Assembly, in the Intel FPGA Monitor Program, for the laboratory work done while attending the McGill Course ECSE 324 Computer Organization

c timer synthesizer fpga-soc interrupt computer-organization timer-clock vga-driver assembly-x86 ps2-keyboard-interface altera-de1 arm-cortex-a9

Updated Jan 3, 2022
Assembly

Nativu5 / DE1-SoC-MyPlayer

A Music Player on DE1-SoC Board.

fpga cyclone-v altera-de1

Updated Feb 22, 2022
C

EngineerMichael / ModelSim-Altera-Project-Electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

modelsim vhdl-code altera-fpga altera-de1 altera-quartus synchronous-counter

Updated Dec 23, 2024

jxwleong / altera-de1-traffic-light-controller

Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.

fsm fpga verilog altera-de1

Updated Dec 8, 2019
Verilog

jxwleong / altera-de1-processor

Synthesize a general purpose microprocessor (GPM) using verilog hdl code on Altera DE1 development board. The processor was used to find the greatest common divisor (GCD) between two integers.

fpga verilog gcd processors cocotb-testing altera-de1

Updated Oct 10, 2023
Verilog

Chrisdeleon91 / Altera-DE1-VGA-Interface

Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.

fsm vhdl intel finite-state-machine quartus-prime vga-driver vga-controller altera-fpga vhdl-coursework quartus2 altera-de1

Updated Feb 7, 2023
VHDL

Cesarsk / the_snake_game

The Snake Game Made in VHDL for Altera DE1 using Quartus V.13

vhdl quartus altera-de1

Updated Apr 13, 2019
VHDL

anchaides / docker-arm-gnuabihf-de1-soc

Helps with Cross compilation for arm-gnueabihf-gcc linux compilation for the HPS found in cyclone V subsystems on DE1-SOC boards.

fpga-soc altera-de1

Updated Jun 24, 2023
Dockerfile

chkrr00k / hex-controller

Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board

vhdl altera seven-segment vhdl-modules seven-segments-display altera-fpga vhdl-coursework seven-segment-display altera-de1 terasic-de1

Updated Apr 12, 2019
VHDL

inmerso / funky_appliance

Kitchen-timer on Altera DE1 FPGA development kit - VHDL

fpga vhdl altera-de1 cyclone-ii

Updated Nov 23, 2023
VHDL

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