UART Peripheral RTL Design

A comprehensive UART (Universal Asynchronous Receiver-Transmitter) peripheral implementation in VHDL, designed for Artix-7 FPGA. This project provides a full-featured UART communication interface with advanced features including configurable parameters, FIFO buffers, interrupt handling, and loopback testing capabilities.

🚀 Features

Core UART Functionality

• Asynchronous serial communication with full-duplex operation
• Configurable baud rates: 2400, 4800, 9600, 19200 bps
• Flexible data configuration:
  • Data bits: 8-bit or 9-bit
  • Parity: None, Even, Odd
  • Stop bits: 1, 1.5, or 2 bits
• FIFO buffering for both TX and RX channels (configurable depth)
• Interrupt generation with status reporting
• Loopback mode for testing and diagnostics

Advanced Features

• Register-based configuration interface with memory-mapped I/O
• Status monitoring with overflow and underflow detection
• Error detection including parity errors and FIFO violations
• Bidirectional bus interface with proper handshaking
• Clock domain management with proper synchronization

📁 Project Structure

UART_peripheral/
├── source_flies/
│   ├── source_files/          # Main VHDL source files
│   │   ├── wrapper_book.vhd   # Top-level wrapper
│   │   ├── uart_core.vhd      # UART core module
│   │   ├── uart_TX_controller.vhd
│   │   ├── uart_RX_controller.vhd
│   │   ├── baud_gen.vhd       # Baud rate generator
│   │   ├── fifo.vhd           # FIFO implementation
│   │   ├── tx_fsm.vhd         # TX state machine
│   │   ├── parity_gen.vhd     # Parity generator/checker
│   │   ├── reg_file.vhd       # Register file
│   │   └── ...                # Other supporting modules
│   ├── test_bench/            # Verification testbenches
│   │   └── tb_wrap_book.vhd   # Top-level testbench
│   └── constraint_files/      # FPGA constraints
│       └── wrap_uart.xdc      # Timing and pin constraints
├── Uart_Documentation_REPORT.pdf  # Detailed documentation
├── Description_video.mp4      # Project demonstration
└── README.md                  # This file

🏗️ Architecture Overview

System Architecture

The UART peripheral follows a modular design with clear separation of concerns:

1. Top-level Wrapper (wrap_uart)

   • System interface and I/O management
   • Register file interface
   • Interrupt generation
   • Clock and reset distribution

2. UART Core (UART_MODULE)

   • TX/RX controllers
   • FIFO management
   • Baud rate generation
   • Protocol handling

3. Supporting Modules

   • Bidirectional bus interface
   • Address decoder
   • Synchronization blocks
   • Loopback interface

Memory Map

Address	Register	Access	Description
0x1	CTRL	R/W	Control register (baud, parity, stop bits, loopback)
0x2	STAT	R	Status register (FIFO status, errors)
0x4	RX_DATA	R	Receive data register
0x5	TX_DATA	W	Transmit data register

Control Register Format

Bit 7: LOOP_BACK - Loopback mode enable
Bit 6-5: STOP_BITS - Stop bit selection (00=1, 01=1.5, 10=2)
Bit 4-3: BAUD_SEL - Baud rate selection (00=19200, 01=9600, 10=4800, 11=2400)
Bit 2-1: PARITY_TYPE - Parity selection (00=none, 01=even, 10=odd)
Bit 0: D_BITS - Data bits (0=8-bit, 1=9-bit)

🔧 Hardware Requirements

• Target FPGA: Xilinx Artix-7 family
• Development Tools: Xilinx Vivado
• Clock: 50 MHz system clock
• Resources: Minimal LUT and BRAM usage
• I/O Requirements:
  • Serial RX/TX pins
  • System clock and reset
  • Address/data bus interface
  • Interrupt output

🛠️ Usage Instructions

1. Synthesis and Implementation

# Open Vivado and create new project
# Add all source files from source_flies/source_files/
# Add constraint file: source_flies/constraint_files/wrap_uart.xdc
# Set wrap_uart as top module
# Run synthesis and implementation

2. Configuration Example

-- Configure for 9600 baud, 8-bit data, odd parity, 1 stop bit
CTRL_REG <= "00010110";  -- Binary: 00(1 stop) 01(9600) 10(odd) 0(8-bit)

3. Data Transmission

-- Check TX FIFO not full
if TX_FULL = '0' then
    -- Write data to TX register
    write_data(TX_ADDR, data_byte);
end if;

4. Data Reception

-- Check RX FIFO not empty
if RX_EMPTY = '0' then
    -- Read data from RX register
    data_byte := read_data(RX_ADDR);
end if;

🧪 Testing and Verification

Testbench Features

• Comprehensive test scenarios covering all configuration modes
• Loopback testing for end-to-end verification
• Error injection and recovery testing
• Timing verification for different baud rates
• FIFO stress testing with overflow/underflow conditions

Running Tests

# Simulate with ModelSim/Vivado Simulator
# Load testbench: tb_wrap_book.vhd
# Run simulation with appropriate time resolution
# Observe waveforms using provided .wcfg file

📊 Technical Specifications

Performance Characteristics

• Maximum Clock Frequency: 100 MHz+
• Baud Rate Accuracy: ±0.5% for all supported rates
• FIFO Depth: Configurable (default: 4 words)
• Data Width: 8 or 9 bits (configurable)
• Interrupt Latency: 2-3 clock cycles

Resource Utilization (Artix-7)

• LUTs: ~150-200 (varies with configuration)
• Flip-Flops: ~100-150
• Block RAM: 1-2 blocks (for FIFOs)
• I/O Pins: ~15-20

🔍 Key Design Decisions

1. Modular Architecture: Enables easy customization and maintenance
2. FIFO Integration: Reduces software overhead and improves throughput
3. Configurable Parameters: Single design supports multiple use cases
4. Interrupt Support: Enables efficient CPU utilization
5. Error Detection: Comprehensive error reporting for robust operation

📚 Documentation

• Detailed Documentation: See Uart_Documentation_REPORT.pdf for complete design specifications
• Video Tutorial: Watch Description_video.mp4 for project overview and demonstration
• Source Comments: All VHDL files include detailed inline documentation

🤝 Usage and Licensing

This UART peripheral design is an educational/research project developed at IISC (Indian Institute of Science).

Important: Please contact the author (Rishabh Dubey) before using this code in any commercial or academic projects to ensure proper attribution and licensing compliance.

📧 Contact

Engineer: Rishabh Dubey
Institution: Indian Institute of Science (IISC)
Project: UART Peripheral RTL Design
Target: Artix-7 FPGA

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For detailed implementation information, refer to the documentation PDF and source code comments. The description video provides a comprehensive walkthrough of the design and its features.