Discussions

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  Required SRAM size for CVA6

  AAnand-Git asked Sep 13, 2024 in Q&A · Unanswered

  

  

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  Welcome to CVA6 Discussions!

  zarubaf started Dec 14, 2020 in General

  

  

  

  

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  Steps to run bare metal code on implemented CVA6 core

  yadu-kr asked Dec 21, 2023 in Q&A · Unanswered

  

  

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  Creating Vivado project

  kristopher391 asked Sep 12, 2023 in Q&A · Unanswered

  

  

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  Seeking explanation of some variable in Makefile!

  AnikBalo asked Jun 8, 2023 in Q&A · Unanswered

  

  

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  How can I generate VCD while performing cva6 rtl simulation in questasim?

  AnikBalo asked May 23, 2023 in Q&A · Unanswered

  

  

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  Is the hypervisor extension functional in the feat/hyp-upstream branch?

  Teofil98 asked May 20, 2023 in Q&A · Unanswered

  

  

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  Illegal instruction at start of ram during Questa simulation

  artakarakelyan asked Dec 14, 2022 in Q&A · Answered

  

  

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  create IP core from github code

  jimaandro asked Mar 5, 2023 in Q&A · Closed · Unanswered

  

  

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  How to use uart for printf and other console output calls in bare metal program?

  artakarakelyan asked Dec 25, 2022 in Q&A · Unanswered

  

  

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  Crash when trying to connect openocd to simulation

  artakarakelyan asked Dec 20, 2022 in Q&A · Unanswered

  

  

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  Problem when Make Verilate

  Aleone7 asked Oct 17, 2022 in Q&A · Unanswered

  

  

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  Floating point support ?

  gent-bujupaj asked Aug 18, 2022 in Q&A · Unanswered

  

  

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  Performance Monitoring of the Processor Core

  mashahedurrahman asked Mar 14, 2022 in Q&A · Unanswered

  

  

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  Targeting Other FPGA Boards

  RB-Finch asked Jan 11, 2022 in Q&A · Unanswered

  

  

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  What's the status on vcu118 support?

  michael-etzkorn asked Aug 20, 2021 in Q&A · Unanswered

  

  

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  Cache_ctrl.sv

  Simonlovald asked May 28, 2021 in Q&A · Unanswered

  

  

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  clint_tick dpi could not find in ariane_dpi.so with spike

  zhouyongzhong-zxw asked Apr 26, 2021 in Q&A · Unanswered

  

  

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  Build the Verilator model of Ariane by using the Makefile

  2536786901 asked Apr 11, 2021 in Q&A · Unanswered

  

  

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  AXI4 interface connects to AXI4-lite in clint

  jimmysitu asked Nov 25, 2020 in Q&A · Unanswered

  

  

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  Requirements for test cases that will run in the cva6/verilator simulation environment?

  mtvaden asked Aug 20, 2020 in Q&A · Unanswered

  

  

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