Merge cv32e40x/dev to cv32e40x/release

.gitignore

@@ -35,3 +35,4 @@ cva6/tests/riscv-compliance/
 cva6/tests/riscv-tests/
 uvm/riscv-dv/
 riviera_results/
+*/vendor_lib/dpi_dasm_spike/

.metrics.json

@@ -8,26 +8,26 @@
       {
         "name":     "uvmt_cv32e40p",
         "image":    "cv32-simulation-tools:20200720.11.0-19102020",
-        "cmd":      "cd cv32e40p/sim/uvmt; make corev-dv CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40p SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40p/sim/uvmt; make corev-dv CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40p SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40p/sim/uvmt; make corev-dv CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40p/sim/uvmt; make corev-dv CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40p_compliance_build",
         "image":    "cv32-simulation-tools:20200720.11.0-19102020",
-        "cmd":      "cd cv32e40p/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40p SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40p/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40p SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40p/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40p/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x",
         "image":    "cv32-simulation-tools:20200720.11.0-19102020",
-        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
       },
       {
         "name":     "uvmt_cv32e40x_compliance_build",
         "image":    "cv32-simulation-tools:20200720.11.0-19102020",
-        "cmd":      "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
-        "wavesCmd": "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
+        "cmd":      "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
+        "wavesCmd": "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1"
       }
     ]
   },

bin/README.md

@@ -44,9 +44,13 @@ simulator for the purposes of ensuring a pull-request can be safely made.  Note
 be able to be executed in any directory where previously it required the user to *cd* to ci/.  Please 
 refer to *ci_check*'s help utility for more details on options
 
+If required, the step and compare ISS can be disabled for this regression by setting _--iss=0_
+
 *Examples:*
 > \# Run CI sanity regression on Xcelium<br>
 % ci_check -s xrun<br>
+> \# Run CI sanity regression on Xcelium with the ISS disabled<br>
+% ci_check -s xrun --iss=0<br>
 > \# Get help of all available options<br>
 % ci_check --help
 

bin/cfgyaml2make

@@ -79,7 +79,13 @@ def read_file(file):
 
     stream = open(matches[0], 'r')
     logger.debug('Reading cfg specification: {}'.format(matches[0]))
-    cfg_spec = yaml.load(stream)
+    # Newer PyYAMLs must specify explicit loader (policy) or will issue warnings
+    # Older PyYAMLs will not support the Loader argument
+    # So try the new way first, then catch to the old way
+    try:
+        cfg_spec = yaml.load(stream, Loader=yaml.FullLoader)
+    except AttributeError:
+        cfg_spec = yaml.load(stream)
     stream.close()
 
     # Validation

bin/ci_check

@@ -79,6 +79,7 @@ parser.add_argument("-c", "--check_only",    help="Check previosu results (do no
 parser.add_argument("-k", "--keep",          help="Keep previous cloned or generated files",          action="store_true")
 parser.add_argument("-v", "--verilator",     help="Run Verilator on the CORE testbench",              action="store_true")
 parser.add_argument("-u", "--no_uvm",        help="DO NOT run CI regression on the UVM testbench",    action="store_true")
+parser.add_argument('--iss',                 help='Force USE_ISS flag to each test run (use 0 or 1), default: Enabled')
 parser.add_argument("--repo",                help="Use this repo for the RTL, not one in Makefile",   type=str)
 parser.add_argument("--branch",              help="Use this branch for the RTL, not one in Makefile", type=str)
 parser.add_argument("--hash",                help="Use this hash for the RTL, not one in Makefile",   type=str)
@@ -183,7 +184,13 @@ def load_regress_yaml(regression):
     '''Load the regression yaml and return the dictionary'''
     full_regression = os.path.join(topdir, '{}/regress'.format(args.core.lower()), regression + '.yaml')
     fh = open(full_regression, 'r')
-    dict = yaml.load(fh)
+    # Newer PyYAMLs must specify explicit loader (policy) or will issue warnings
+    # Older PyYAMLs will not support the Loader argument
+    # So try the new way first, then catch to the old way
+    try:
+        dict = yaml.load(fh, Loader=yaml.FullLoader)
+    except AttributeError:
+        dict = yaml.load(fh)
     fh.close()
 
     return dict
@@ -339,10 +346,16 @@ if (uvm):
                     except KeyError:
                         num = 1
 
-                    try:                    
-                        iss = key['iss']
-                    except KeyError:
-                        iss = 1
+                    # The iss command-line switch takes precedence,
+                    # Otherwise use what is in the regression yaml if defined
+                    # Otherwise set to 1                    
+                    if args.iss != None:
+                        iss = int(args.iss)
+                    else:
+                        try:                    
+                            iss = key['iss']
+                        except KeyError:
+                            iss = 1
 
                     for n in range(num):                    
                         # Add directory

bin/cv_regress

@@ -80,7 +80,14 @@ def is_test_indexed(project, name):
     for t in test_dirs:
         test_yaml = os.path.join(t, name, 'test.yaml')
         if os.path.exists(test_yaml):
-            test_spec = yaml.load(open(test_yaml))            
+            # Newer PyYAMLs must specify explicit loader (policy) or will issue warnings
+            # Older PyYAMLs will not support the Loader argument
+            # So try the new way first, then catch to the old way
+            try:
+                test_spec = yaml.load(open(test_yaml), Loader=yaml.FullLoader)
+            except AttributeError:
+                test_spec = yaml.load(open(test_yaml))
+
             if '<RUN_INDEX>' in test_spec['name']:
                 return True
             else:
@@ -104,8 +111,14 @@ def read_file(args, file):
     '''Read a YAML definition filelist'''
     full_regress_file = os.path.join(get_regress_path(args.project), file)
     stream = open(full_regress_file, 'r')
-    logger.info('Reading regression: {}'.format(full_regress_file))
-    testlist = yaml.load(stream)
+    logger.info('Reading regression: {}'.format(full_regress_file))    
+    # Newer PyYAMLs must specify explicit loader (policy) or will issue warnings
+    # Older PyYAMLs will not support the Loader argument
+    # So try the new way first, then catch to the old way
+    try:
+        testlist = yaml.load(stream, Loader=yaml.FullLoader)
+    except AttributeError:
+        testlist = yaml.load(stream)
     stream.close()
     pp = pprint.PrettyPrinter()
     logger.debug('Read YAML:')
@@ -152,6 +165,8 @@ def read_file(args, file):
             test.set_cov()
         if args.make:
             test.sub_make(args.make)
+        if args.iss != None:            
+            test.iss = args.iss
 
         # Determine if a test is valid, skip for compliance tests
         # Since it is not possible to determine apriori if a compliance test is valid
@@ -173,6 +188,7 @@ DEFAULT_SIMULATOR = 'dsim'
 VALID_PROJECTS = ('cv32e40p', 'cv32e40x', 'cv64')
 DEFAULT_PROJECT = 'cv32e40p'
 DEFAULT_CFG = 'default'
+DEFAULT_PARALLEL = '30'
 
 logging.basicConfig(level=logging.INFO)
 logger = logging.getLogger(__name__)
@@ -185,6 +201,8 @@ parser.add_argument('-d', '--debug', help='Emit debug messages from logger', act
 parser.add_argument('-s', '--simulator', help='Select simulator', choices=VALID_SIMULATORS, default=DEFAULT_SIMULATOR)
 parser.add_argument('-c', '--cov', help='Enable coverage', action='store_true')
 parser.add_argument('--cfg', default=DEFAULT_CFG, help='Test configuration to test')
+parser.add_argument('--iss', default=None, help='Force USE_ISS flag to each test run')
+parser.add_argument('--parallel', default=DEFAULT_PARALLEL, help='For VSIF only, set number of parallel jobs')
 parser.add_argument('-m', '--metrics', help='Select Metrics waves output', action='store_true')
 parser.add_argument('-n', '--num', help='Force number of iterations for tests with multiple iteration')
 parser.add_argument('--lsf', help='If applicable for output format, set LSF args to dispatch jobs')
@@ -266,6 +284,7 @@ if args.vsif:
     out_fh.write(template.render(session=os.path.splitext(os.path.basename(args.outfile))[0],
                                  results_path=get_results_path(args.project),
                                  project=args.project,
+                                 parallel=args.parallel,
                                  cfg=args.cfg,
                                  regressions=regressions,
                                  makeargs=' '.join(args.makearg) if args.makearg else '',

bin/run_embench.py

@@ -39,6 +39,7 @@
 import sys
 import subprocess
 import jinja2
+import glob
 import re
 
 
@@ -216,7 +217,10 @@ def main():
   #Check if benchmark run succeeded
   if not run_passed(res.stdout, args.type):
     logging.fatal(f"EMBench benchmark run failed")
-
+    log_file = get_log_file(args.core, paths, args.type)
+    if log_file:
+        logging.info('For more debug check EMBench log: {}'.format(log_file))
+    sys.exit(1)
 
   if check_result(res.stdout, args.target, args.type) and args.target != 0:
     print(f"Benchmark run met target")
@@ -324,6 +328,7 @@ def build_paths(core):
   paths['libcfg'] = paths['core'] + '/tests/embench/config/corev32'
   paths['libpy'] = paths['core'] + '/tests/embench/pylib'
   paths['vlib'] = paths['core'] + '/vendor_lib'
+  paths['emb_logs'] = paths['core'] + '/vendor_lib/embench/logs'
   paths['make'] = paths['core'] + '/sim/uvmt'
   paths['embench'] = paths['vlib'] + '/embench'
   paths['emcfg'] = paths['embench'] + '/config/corev32'
@@ -390,6 +395,17 @@ def check_python_version(major, minor):
         log.error('ERROR: Requires Python {mjr}.{mnr} or later'.format(mjr=major, mnr=minor))
         sys.exit(1)
 
+def get_log_file(core, paths, log_type):
+    '''Find the log file from EMBench by looking for the latest touched file'''
+    last_mtime = 0
+    file = None    
+    for f in glob.glob(os.path.join(paths['emb_logs'], '{}-*.log'.format(log_type))):
+        if last_mtime < os.stat(f).st_mtime:
+            last_mtime = os.stat(f).st_mtime
+            file = f
+
+    print('Latest log = {}'.format(file))
+    return file
 
 #run main
 if __name__ == '__main__':

bin/templates/metrics.json.j2

@@ -24,8 +24,8 @@
 
 {% import 'regress_macros.j2' as regress_macros %}
 
-{% set common_dsim_make_vars = "CV_CORE=" + project + " DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results" %}
-{% set common_dsim_make_vars_waves = "CV_CORE=" + project + " DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1" %}
+{% set common_dsim_make_vars = "CV_CORE=" + project + " COMP=0 DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results" %}
+{% set common_dsim_make_vars_waves = "CV_CORE=" + project + " COMP=0 DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1" %}
 [
 {% for r in regressions %}
 {% for t in r.tests.values()|sort(attribute='name') %}

bin/templates/regress_macros.j2

@@ -1,3 +1,3 @@
 {%- macro yesorno(val) -%}
-{%- if val -%}YES{%- else -%}NO{%- endif -%}
+{%- if val == '0' -%}NO{%- elif val == '1' -%}YES{%- elif val == True-%}YES{%- else -%}{{val}}{%- endif -%}
 {%- endmacro -%}

bin/templates/regress_sh.j2

@@ -62,7 +62,7 @@ incr_test_counts () {
 
 {% for b in unique_builds.values() %}
 # Build:{{b.name}} {{b.description}}
-{% set cmd = b.cmd + ' CV_CORE=' + project + ' CFG=' + cfg + ' SIMULATOR=' + b.simulator + ' USE_ISS=' + regress_macros.yesorno(b.iss) + ' COV=' + regress_macros.yesorno(b.cov) + makeargs %}
+{% set cmd = b.cmd + ' CV_CORE=' + project + ' CFG=' + cfg + ' SIMULATOR=' + b.simulator + ' COV=' + regress_macros.yesorno(b.cov) + makeargs %}
 echo "{{session}}: Running build: [cd {{b.abs_dir}} && {{cmd}}]"
 pushd {{b.abs_dir}} > /dev/null
 {{cmd}}

bin/templates/regress_vsif.j2

@@ -27,19 +27,19 @@ session {{session}} {
     top_dir: {{results_path}}/vmgr_sessions;
 {% if lsf %}
     drm: lsf;
-    max_runs_in_parallel: 30;
+    max_runs_in_parallel: {{parallel}};
     queuing_policy: round_robin;
     default_dispatch_parameters: <text>{{lsf}}</text>;
 {% endif %}
 }
 
-group cv32e40p {
+group {{project}} {
 {% if sve %}
     sve_name: {{sve}};
 {% endif %}
 {% for b in unique_builds.values() %}
     // Build:{{b.name}} {{b.description}}    
-    pre_group_script: 'cd {{b.abs_dir}} && {{b.cmd}} CV_CORE={{project}} CFG={{cfg}} CV_SIM_PREFIX= SIMULATOR={{b.simulator}} USE_ISS={{b.iss}} COV={{regress_macros.yesorno(b.cov)}} {{makeargs}}';
+    pre_group_script: 'cd {{b.abs_dir}} && {{b.cmd}} CV_CORE={{project}} CFG={{cfg}} CV_SIM_PREFIX= SIMULATOR={{b.simulator}} COV={{regress_macros.yesorno(b.cov)}} {{makeargs}}';
 
 {% endfor %}
 {% for r in regressions %}

bin/yaml2make

@@ -85,7 +85,13 @@ def read_file(test, type, run_index):
 
     stream = open(matches[0], 'r')
     logger.debug('Reading test specification: {}'.format(matches[0]))
-    test_spec = yaml.load(stream)
+    # Newer PyYAMLs must specify explicit loader (policy) or will issue warnings
+    # Older PyYAMLs will not support the Loader argument
+    # So try the new way first, then catch to the old way
+    try:
+        test_spec = yaml.load(stream, Loader=yaml.FullLoader)
+    except AttributeError:
+        test_spec = yaml.load(stream)
     stream.close()
     test_spec['test_dir'] = os.path.dirname(matches[0])
 
@@ -123,12 +129,12 @@ def emit_make(test_spec, prefix):
 # Command-line arguments
 
 parser = argparse.ArgumentParser()
-parser.add_argument('-t', '--test', help='Test to look for')
-parser.add_argument('-d', '--debug', action='store_true', help='Display debug messages')
-parser.add_argument('--yaml', choices=VALID_YAMLS, help='Name of YAML test specification to find')
-parser.add_argument('--prefix', help='Prefix to add to make variables generated')
+parser.add_argument('-t', '--test', help='Required: Test to look for')
+parser.add_argument('--yaml', choices=VALID_YAMLS, help='Required: Name of YAML test specification to find')
 parser.add_argument('--core', default=DEFAULT_CORE, help='Default core to test')
+parser.add_argument('--prefix', help='Prefix to add to make variables generated')
 parser.add_argument('--run-index', default='0', help='Add a run index to append to test specifications')
+parser.add_argument('-d', '--debug', action='store_true', help='Display debug messages')
 args = parser.parse_args()
 
 if args.debug:

cv32e40p/tests/embench/README.md

@@ -89,10 +89,22 @@ unique files, dependencies in the core specific makefiles also exist.
 Copy the embench configuration directory from cv32e40p to the new core:
 >/core-v-verif/\[core\]/tests/embench
 
+Copy the embench makefile defines(EMBENCH_*) from cv32e40p to the new core:
+>/core-v-verif/\[core\]/sim/Common.mk
+
 Copy over the embench directory under *programs*. This should be empty except for a readme file.
 >/core-v-verif/\[core\]/tests/programs/embench
 
-If there are no differences in configuration necessary compared to the cv32e40p, you are now done, and can
+
+Make the following changes to the .gitignore files listed:<br>
+| File                                         | Add line |
+|----------------------------------------------|----------|
+| /core-v-verif/\[core\]/tests/.gitignore      | emb_*/   |
+| /core-v-verif/\[core\]/vendor_lib/.gitignore | embench/ |
+
+
+
+<br>If there are no differences in configuration necessary compared to the cv32e40p, you are now done, 
 run the EMBench scripts in the manner described above. However, if there are notable differences, 
 a quick description on what to check follows. For full details, please check the EMBench [documentation](https://github.com/embench/embench-iot/blob/master/doc/README.md).<br>