Merge pull request #584 from strichmo/cv32e40p/merge_dev_to_rel_5

merge from cv32e40p/dev to cv32e40p/release
openhwgroup · May 5, 2021 · 50cac35 · 50cac35
2 parents 6eee088 + 49a67f1
commit 50cac35
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Showing 4 changed files with 12 additions and 6 deletions.
diff --git a/cv32e40p/vendor_lib/imperas/riscv_CV32E40P_OVPsim/README.md b/cv32e40p/vendor_lib/imperas/riscv_CV32E40P_OVPsim/README.md
@@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable CV32E40P Simulation Model
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 20210209 
-Version: 20200821.11  
+Date   : 20210422 
+Version: 20200821.12  
 License: Simulation Model CV32E40P licensed under [Software License Agreement for Open Virtual Platforms Technology](OVP_IMPERAS_LICENSE.pdf)
 RISC-V Specifications currently supported:
 - RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.3)
@@ -61,7 +61,7 @@ About Open Virtual Platforms (OVP) and Imperas Software
 [www.imperas.com](http://www.imperas.com/riscv).
 
 ![OVP Image ](http://www.imperas.com/sites/default/files/partner-logos/ovp_0.jpg)  
-![Imperas Imperas](http://www.imperas.com/sites/all/themes/tophit/logo.png)  
+![Imperas Imperas](https://www.imperas.com/sites/default/files/imperas-web-logo_2.png)  
 ---
 
 

diff --git a/cv32e40p/vendor_lib/imperas/riscv_CV32E40P_OVPsim/bin/Linux64/riscv_CV32E40P.dpi.so b/cv32e40p/vendor_lib/imperas/riscv_CV32E40P_OVPsim/bin/Linux64/riscv_CV32E40P.dpi.so
diff --git a/...s/riscv_CV32E40P_OVPsim/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf b/...s/riscv_CV32E40P_OVPsim/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf
diff --git a/cv32e40p/vendor_lib/imperas/riscv_CV32E40P_OVPsim/sv/riscv_CV32E40P.sv b/cv32e40p/vendor_lib/imperas/riscv_CV32E40P_OVPsim/sv/riscv_CV32E40P.sv
@@ -129,6 +129,8 @@ module CPU
 
     // From RTL
     bit [31:0] GPR_rtl[32];
+    bit [31:0] cycles;
+
 /*
     always @state.notify begin
         if (state.valid) begin
@@ -237,14 +239,18 @@ module CPU
             output int _deferint,
             output int _irq_i,
             output int _haltreq,
-            output int _resethaltreq);
+            output int _resethaltreq,
+            output int _cycles
+            );
 
         _terminate          = SysBus.Shutdown;
         _reset              = SysBus.reset;
         _deferint           = SysBus.deferint;
         _irq_i              = SysBus.irq_i;
-        _haltreq            = SysBus.haltreq ;
-        _resethaltreq       = SysBus.resethaltreq ;
+        _haltreq            = SysBus.haltreq;
+        _resethaltreq       = SysBus.resethaltreq;
+
+        _cycles             = cycles;
     endfunction
 
     function automatic void setDECODE (input string value, input int insn, input int isize);