Bump third_party/litex from e07bd7 to dcae61 #13

dependabot-preview · 2017-11-02T07:14:12Z

Bumps third_party/litex from e07bd7 to dcae61.

Commits

Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting @dependabot rebase?.

If you'd like to skip this version, you can just close this PR. If you have any feedback just mention @dependabot in the comments below.

Bumps [third_party/litex](https://github.com/enjoy-digital/litex) from e07bd7 to dcae61. - [Commits](enjoy-digital/litex@e07bd71...dcae61b)

dependabot-preview · 2017-11-09T07:11:38Z

Superseded by #18.

arty: Support "make firmware-load" for F=micropython

* flash_proxies changed from 070d8b2 to c506426 * c506426 - Merge pull request #3 from cr1901/master <Robert Jördens> * bf63a40 - Add Spartan 7 (xc7s50) bitstream, plus corresponding logic to regenerate. <William D. Jones> * litedram changed from a09b7a0 to 13d41f6 * 13d41f6 - Merge pull request #9 from felixheld/indentation-fixes <Tim Ansell> * 72b1b10 - Fix all remaining indentation issues in python code <Felix Held> * litepcie changed from 09dbd6d to 945963d * 945963d - phy/s7pciephy: set sys_rst_n to 1 if no rst_n pad <Florent Kermarrec> * 5590f11 - Merge pull request #7 from felixheld/indentation-fixes <Tim Ansell> |\ | * d602010 - Fix all remaining indentation issues in python code <Felix Held> * 9469929 - Merge pull request #6 from felixheld/indentation-fixes <Tim Ansell> * 5376257 - fix code indentation <Felix Held> * litesata changed from a8bf0d4 to af00fa6 * af00fa6 - Merge pull request #13 from felixheld/indentation-fixes <Tim Ansell> * 220b601 - Fix all indentation issues in python code <Felix Held> * litescope changed from 7757727 to aa44da3 * aa44da3 - example_designs/make.py: fix typos <Florent Kermarrec> * 72e71e7 - core: simplify <Florent Kermarrec> * 7803591 - Merge pull request #9 from felixheld/indentation-fixes <Tim Ansell> * febb358 - Fix all remaining indentation issues in python code <Felix Held> * liteusb changed from 9a78586 to 0b05b6c * 0b05b6c - +x on scripts <Florent Kermarrec> * litevideo changed from c9770cc to 8d940dc * 8d940dc - output: add raw support (10 bits tmds in dram), untested <Florent Kermarrec> * 5c168aa - input: add capability to get raw 10 bits data when not using dram port <Florent Kermarrec> * dcd9624 - input/edid: simplify scl inversion <Florent Kermarrec> * 3b04d1b - Merge pull request #14 from bunnie/scl-merge <enjoy-digital> |\ | * 7845c85 - add inverted attribute to SCL <bunnie> |/ * a7fd5f6 - Merge pull request #13 from felixheld/indentation-fixes <Tim Ansell> |\ | * 34b1a0f - Fix all remaining indentation issues in python code <Felix Held> |/ * 4d6bc46 - input/datacapture: simplify inverted data in S7DataCapture <Florent Kermarrec> * af096a5 - input/clocking/s7: use bufr and fix input connection to mmcm <Florent Kermarrec> * 9ebdd1b - output: use new inverted property of pads to invert polarity <Florent Kermarrec> * 218b708 - output: add assertion if inverted property is used (since not yet implemented) <Florent Kermarrec> * 113bdb7 - input: use new inverted property of pads to invert polarity <Florent Kermarrec> * 091c9ec - litevideo: add __init__.py, fix install <Florent Kermarrec> * 9aae319 - input: add clk_polarity parameter, rename data_polarities to datas_polarity <Florent Kermarrec> * litex changed from v0.1-251-gead88ed6 to v0.1-270-g4f272580 * 4f272580 - software/common: revert PYTHON to python3 (since breaking things) <Florent Kermarrec> * 4e168221 - bios: fix riscv processor print <Florent Kermarrec> * d4488748 - sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) <Florent Kermarrec> * a3851437 - Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives <enjoy-digital> |\ | * 21bd26dc - Allow for multiple synthesis directives in specials. <Sergiusz Bazanski> |/ * 67f8718b - minor cleanup <Florent Kermarrec> * d07ddd11 - Merge pull request #58 from q3k/for-upstream/picorv32-support <enjoy-digital> |\ | * 6daf3eab - Implement IRQ software support for RISC-V. <Sergiusz Bazanski> | * 2108c97b - Import PicoRV32-specific instruction macros. <Sergiusz Bazanski> | * cf74c781 - Write init files that respect CPU's endianness. <Sergiusz Bazanski> | * 71764922 - Set the MABI and MArch of the riscv target. <Sergiusz Bazanski> | * 7ea5a267 - Enable hardware multiplier and divider in PicoRV32 <Sergiusz Bazanski> | * 75e230aa - Replace __riscv__ macros with __riscv. <Sergiusz Bazanski> | * 20ed2344 - Export trap signal from PicoRV32. <Sergiusz Bazanski> | * b0be5630 - Bump PicoRV32 version. <Sergiusz Bazanski> |/ * 3a5f93db - software/bios: add litex logo <Florent Kermarrec> * d6877300 - Merge pull request #56 from cr1901/mimasv2 <enjoy-digital> |\ | * c553fe2b - Add mimasv2 platform (pulled from litex-buildenv). <William D. Jones> |/ * d6f2f637 - Merge pull request #53 from mithro/allow-forcing-colorama <Tim Ansell> Full submodule status -- f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master) c5064269868396b2c7a78bff28f8e3cf421d1f6e flash_proxies (remotes/origin/HEAD) 13d41f67ab3070f6af955aa8752c616d034f82f6 litedram (remotes/origin/HEAD) 8fc716103670e703c7fe98c9bdf653b9b53ca12a liteeth (remotes/origin/HEAD) 945963d186b3c0287426ef6655e00ad4e250d279 litepcie (remotes/origin/HEAD) af00fa613f1b6921e14788dd0ebf301e51009e74 litesata (remotes/origin/HEAD) aa44da35c6a232a9e39c43987a3afc9b025ab614 litescope (remotes/origin/HEAD) 0b05b6c8f9279bb7e476b2c8ae4f39ea88534f08 liteusb (remotes/origin/HEAD) 8d940dcaf21cffb18cd157e079ec94946878a5d7 litevideo (remotes/origin/HEAD) 4f2725809e0b9b6cee94cb569c1878f48ab52a15 litex (v0.1-270-g4f272580)

* flash_proxies changed from c506426 to a628956 * a628956 - Merge pull request #4 from cr1901/more-series7 <Robert Jördens> * 8be7e2d - Add new bitstream proxies for devices available as of Vivado 2017.4.1. <William D. Jones> * 29d9124 - Add new packages for missing Series 7 family members. <William D. Jones> * c1d8007 - Add missing Series 7 family members. <William D. Jones> * litedram changed from 13d41f6 to 48bc3cb * 48bc3cb - README: add migen dependency <Florent Kermarrec> * 697f46a - replace litex.gen imports with migen imports <Florent Kermarrec> * bd43fd6 - bump to 0.2.dev <Florent Kermarrec> * 45a948d - uniformize litex cores <Florent Kermarrec> * 5838953 - modules: add MT47H64M16 <Florent Kermarrec> * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec> * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec> * liteeth changed from 8fc7161 to 33afda7 * 33afda7 - README: add migen dependency <Florent Kermarrec> * 79a6ba7 - replace litex.gen imports with migen imports <Florent Kermarrec> * c15f089 - bump to 0.2.dev <Florent Kermarrec> * c42aa09 - uniformize litex cores <Florent Kermarrec> * 4e08d6e - Merge pull request #13 from felixheld/crc_pythonize <enjoy-digital> * 9dcc7bc - mac/crc.py: make crc calculation more pythonic <Felix Held> * 2ceaa74 - clarify the comments in mac/crc.py code <Felix Held> * litepcie changed from 945963d to 6b147e1 * 6b147e1 - frontend/dma: add 16 bits control field to descriptors <Florent Kermarrec> * 08a4501 - README: add migen dependency <Florent Kermarrec> * 6afbd1c - frontend/dma/LitePCIeDMAWriter: switch to next decriptor when sink.last is asserted <Florent Kermarrec> * ed0b8a4 - phy/xilinx/7-series: integrate v3.3 files (working for x2) <Florent Kermarrec> * d9b8b2a - core/tlp/packetizer: add 128 bits support <Florent Kermarrec> * 686da6b - core/tlp/depacketizer: add 128 bits support <Florent Kermarrec> * 0724533 - replace litex.gen imports with migen imports <Florent Kermarrec> * 3e38b54 - bump to 0.2.dev <Florent Kermarrec> * 96cdfe6 - revert phy to 3.0 and tlp packetizer/depacketizer to fixed 64 bit version (until we investigate the regression) <Florent Kermarrec> * d7d9e5f - uniformize litex cores <Florent Kermarrec> * 058c493 - phy/xilinx/7-series: update to 3.3 <Florent Kermarrec> * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec> * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec> * 4609a88 - test/model/phy: fix typo <Florent Kermarrec> * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec> * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec> * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec> * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec> * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec> * litesata changed from af00fa6 to a559afb * a559afb - README: add migen dependency <Florent Kermarrec> * c1e1341 - replace litex.gen imports with migen imports <Florent Kermarrec> * eafaf16 - bump to 0.2.dev <Florent Kermarrec> * a6c08ce - uniformize litex cores <Florent Kermarrec> * litescope changed from aa44da3 to 9d5e605 * 9d5e605 - replace litex.gen imports with migen imports <Florent Kermarrec> * 302a484 - bump to 0.2.dev <Florent Kermarrec> * 62c4bdd - uniformize litex cores <Florent Kermarrec> * 985585f - __init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports <Florent Kermarrec> * liteusb changed from 0b05b6c to 23d6a68 * 23d6a68 - README: add migen dependency <Florent Kermarrec> * 102a751 - replace litex.gen imports with migen imports <Florent Kermarrec> * 3faa9ae - bump to 0.2.dev <Florent Kermarrec> * d52cf32 - uniformize litex cores <Florent Kermarrec> * litevideo changed from 9907975 to 18b88df * 18b88df - input/edid: fix scl polarity <Florent Kermarrec> * a3c1984 - README: add migen dependency <Florent Kermarrec> * 152b6d7 - replace litex.gen imports with migen imports <Florent Kermarrec> * c96ef9c - bump to 0.2.dev <Florent Kermarrec> * 2274b01 - uniformize litex cores <Florent Kermarrec> * 50e8ac9 - output/VGAPHY: add missing self.sink.ready.eq(1) <Florent Kermarrec> * a7e289a - make split-clocking optional, also make output stage PLLE2 + BUFG <bunnie> * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec> * 61fa158 - Merge pull request #16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell> * 96fdbec - Merge pull request #15 from bunnie/try_florent_720p <enjoy-digital> * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie> * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie> * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie> * litex changed from 4f272580 to 3e7cc255 * 3e7cc255 - Merge pull request #69 from mithro/conda-support <enjoy-digital> |\ | * 3bf50479 - travis: Adding some color. <Tim 'mithro' Ansell> | * 083c2613 - travis: Move the conda install into script so it can be folded. <Tim 'mithro' Ansell> | * da3189c8 - travis: Making the output more readable. <Tim 'mithro' Ansell> | * 12bb3ebf - travis: Build all the SoCs (without gateware). <Tim 'mithro' Ansell> | * e65c121a - Adding a travis config which tests the conda environment still works. <Tim 'mithro' Ansell> | * 795e8285 - Adding conda environment example. <Tim 'mithro' Ansell> |/ * ab2a3277 - Merge pull request #67 from cr1901/vivado-paths <enjoy-digital> |\ | * 2b00b7eb - xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. <William D. Jones> * | db20df49 - Merge pull request #65 from cr1901/tinyfpga-serial <enjoy-digital> |\ \ | * | e71593d6 - platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it optional via `add_extension`. <William D. Jones> * | | fa6b2561 - build/xilinx/platform: fix merge <Florent Kermarrec> * | | 87d4af0b - Merge pull request #66 from cr1901/arty_s7 <Tim Ansell> |\ \ \ | * | | d40c5773 - boards/arty_s7: Fix IOStandard on System Clock. <William D. Jones> |/ / / * | | 7bd718eb - README: add migen installation to quick start guide <Florent Kermarrec> | |/ |/| * | 0332f73a - build/xilinx/vivado: revert toolchain_path <Florent Kermarrec> * | 2ff50a88 - build: fix merge <Florent Kermarrec> * | 64e4e1ce - build: merge with migen.build 27beffe7 <Florent Kermarrec> * | 0edfd9b9 - boards/kcu105: regroup sfp tx and rx <Florent Kermarrec> |/ * c5be6e26 - README: add section for newcomers <Florent Kermarrec> * f372e8c8 - README: cleanup <Florent Kermarrec> * fb088b79 - README: update, migen is no longer forked <Florent Kermarrec> * 1925ba17 - replace litex.gen imports with migen imports <Florent Kermarrec> * 43164b9a - remove migen fork from litex <Florent Kermarrec> * 212e1a70 - bump to 0.2.dev <Florent Kermarrec> * 64aa4ae4 - uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC <Florent Kermarrec> * aaf09705 - Merge pull request #64 from q3k/q3k/axi4lite <enjoy-digital> |\ | * 688f26cc - Change AXI interface and tidy code <Sergiusz Bazanski> | * 512ed2b3 - Preliminary AXI4Lite CSR bridge support <Sergiusz Bazanski> |/ * 55fc9d2d - Merge pull request #60 from q3k/for-upstream/top-level-module-selection <enjoy-digital> |\ | * ef511e7e - Specify top-level module in Lattice Diemond build script. <Sergiusz Bazanski> | * ef6c517d - Build top module as 'dut' in Verilator and set it as top-level. <Sergiusz Bazanski> * 7b5bd404 - Merge pull request #57 from rohitk-singh/master <enjoy-digital> |\ | * 75e7f950 - BIOS: Flashboot without main ram <Ewen McNeill> * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec> * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec> * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec> * 2ecd1b06 - Merge pull request #61 from PaulSchulz/master <enjoy-digital> |\ | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz> | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz> * c83ae98b - Merge pull request #63 from cr1901/arty_s7 <enjoy-digital> * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones> Full submodule status -- f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 48bc3cb15d17202a19e621acd83d2733190285b2 litedram (remotes/origin/HEAD) 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD) 6b147e1d120a3a062cf2c85e950d358b39edb8eb litepcie (remotes/origin/HEAD) a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD) 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD) 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD) 18b88dfee6bf6f4ab55d196747ca00c6c84c2ef2 litevideo (remotes/origin/HEAD) 3e7cc2554b7dcc578ca86fd881d3523625b888f8 litex (remotes/origin/HEAD)

* litedram changed from 5b02791 to f36bcff * f36bcff - phy/gensdrphy: cleanup/simplify pass <Florent Kermarrec> * da06715 - core/bankmachine: typo <Florent Kermarrec> * ab0d519 - core: change cba_shift parameter to more explicit address_mapping parameter <Florent Kermarrec> * 230ea24 - core: simplify/cleanup pass <Florent Kermarrec> * 94b844d - core/frontend: move crossbar to core <Florent Kermarrec> * 8d24163 - phy/s7ddrphy: use our own bitslip module in fabric <Florent Kermarrec> * 20d7675 - phy/s7ddrphy: add additional_read_latency parameter <Florent Kermarrec> * f11506a - examples/litedram_gen: cleanup pins definition <Florent Kermarrec> * 75b314c - modules: update K4B2G1646F and use timings from datasheet <Florent Kermarrec> * b71ed35 - core/bankmachine: manage tRC <Florent Kermarrec> * 0abb3e4 - modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP) <Florent Kermarrec> * 9a950f0 - ecc: update core/test <Florent Kermarrec> * 8a0d0f0 - phy/s7ddrphy: remove hacky bl8 variant (see #60) <Florent Kermarrec> * 5fe4868 - modules: add trrd to all ddr3 modules <Florent Kermarrec> * dbfa929 - Merge pull request #59 from enjoy-digital/tRRD_Fix <enjoy-digital> |\ | * 5315d27 - tRRD incorrectly specified <john@csquare.ca> |/ * 167c0c9 - remove partial reordering code in master, keep things in bank_reordering branch. <Florent Kermarrec> * 828129e - core/bank_machine: simplify trascon <Florent Kermarrec> * 4fa64c8 - core/bankmachine: remove trccon (activate_allowed not used) <Florent Kermarrec> * feac98f - core/bankmachine: use tXXDController everywhere (better timings) <John Sully> * bce411e - common: move tXXDController to common <John Sully> * fef4701 - core/multiplexer: select all ranks on refresh <Florent Kermarrec> * 3481d45 - core/multiplexer: fix rank_decoder width <Florent Kermarrec> * 3b5a1ff - modules: add K4B1G0446F <Florent Kermarrec> * 48c17ce - modules: fix tWTR regression on MT46H32M32 <Florent Kermarrec> * ad0a1d4 - modules: improve timings definition (keep retro-compatibility with previous definitions) <Florent Kermarrec> * litepcie changed from a09d225 to a8b8048 * a8b8048 - core/tlp/reordering: increase buffering <Florent Kermarrec> * 9578a3c - LICENSE: typo <Florent Kermarrec> * b37065c - Merge pull request #13 from enjoy-digital/reordering <enjoy-digital> * 62d6217 - core/tlp/reordering: use buffered=True <Florent Kermarrec> * 35a4aa8 - core/tlp/reordering: use buffered data fifo to ease timings <Florent Kermarrec> * 288c5f9 - core/tlp/reordering: refactor/simplify <Florent Kermarrec> * 1f39ee2 - core/tlp/controller: use log2_int everywhere <Florent Kermarrec> * litex changed from 6e327cda to 3e189379 * 3e189379 - boards/targets: add versa ecp55g prjtrellis target (experimental) <Florent Kermarrec> * a69197d2 - build/lattice: add initial prjtrellis support <Florent Kermarrec> * 397e3c76 - build/lattice/diamond: use bash on linux <Florent Kermarrec> * d029cd24 - build/lattice: improve special_overrides names (vendor_family) <Florent Kermarrec> * 60665358 - Merge pull request timvideos#114 from mithro/xilinx+yosys <enjoy-digital> |\ | * b200ce99 - Merge branch 'master' into xilinx+yosys <enjoy-digital> | |\ | |/ |/| * | 8c0982a1 - Merge pull request timvideos#118 from mithro/uart-sync <enjoy-digital> |\ \ | * | ba0dd572 - uart: Enable buffering the FIFO. <Tim 'mithro' Ansell> |/ / * | f9167053 - README: improve instructions for litex_sim <Florent Kermarrec> * | e3935b48 - build/sim/verilator: don't use THEADS parameters when threads=1 <Florent Kermarrec> * | a44181e7 - soc_sdram: update litedram <Florent Kermarrec> * | ab6a530a - bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode <Florent Kermarrec> * | b8be9545 - build/xilinx/vivado: enable xpm libraries <Florent Kermarrec> * | ab8cf3e3 - soc/cores/clock: add margin parameter to create_clkout (default = 1%) <Florent Kermarrec> * | 915c2f41 - bios/sdram: improve write/read leveling <Florent Kermarrec> * | deffa603 - platforms/kc705: add ddram_dual_rank <Florent Kermarrec> * | 10624c26 - bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) <Florent Kermarrec> * | 9f083e9b - Merge pull request timvideos#116 from stffrdhrn/sim-uart <enjoy-digital> |\ \ | * | 8877dba7 - sim: serial: Send '\r\n' instead of just '\n' <Stafford Horne> | / * | d1879215 - cpu_interface: fix select_triple when only one specified <Florent Kermarrec> * | 3b27d2ae - soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains <Florent Kermarrec> * | 168b07b9 - soc_core: add csr range check <Florent Kermarrec> * | 6febb682 - Merge pull request timvideos#112 from cr1901/8k-b-evn <enjoy-digital> |\ \ | * | 9a44f08a - build/platforms: Add ice40_hx8k_b_evn from Migen. <William D. Jones> | / * | 9cf4ffb3 - Merge pull request timvideos#113 from stffrdhrn/litex-trivial <enjoy-digital> |\ \ | * | ff6de429 - Fix help for or1k builds <Stafford Horne> | * | dafdb8df - Fix compiler warnings from GCC 8.1 <Stafford Horne> |/ / * | 2be52054 - build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) <Florent Kermarrec> | * ace97624 - build.xilinx: Convert attributes to something Yosys understands. <Tim 'mithro' Ansell> | * 78414c05 - xilinx/viviado: Allow yosys for synthesis. <Tim 'mithro' Ansell> | * d13ac3b3 - cpu/mor1kx: Adding verilog include directory. <Tim 'mithro' Ansell> | * dc7cd757 - build.xilinx: Run `phys_opt_design` and generate timing report. <Tim 'mithro' Ansell> |/ * 948527b0 - cores/cpu: revert vexriscv (it seems there is a regression in last version) <Florent Kermarrec> * 15bca453 - targets/sim: fix integrated_main_ram_size when with_sdram <Florent Kermarrec> * migen changed from 0.6.dev-173-gd3b875b to 0.6.dev-179-g657c0c7 * 657c0c7 - class TSTriple: width is the width of the base signal <Staf Verhaegen> * 2d62c0c - platforms/ice40_up5k_b_evn: Add I/O connector and some default I/O (including spiflash). <William D. Jones> * ea6e483 - Fix issue where BusSynchronizer fails when iclock << oclock <bunnie> * 076ec0d - fhdl.visit: fix nondeterminism in visit_Case. <whitequark> * 1e114c7 - add a print to show user context when an exception is raised while evaluating a generator yield statement in simulation <N. Engelhardt> * ba63364 - platforms/ice40_hx8k_b_evn: Add pins for spiflash io. <William D. Jones> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) f36bcff49fe96867503c219dd705ff8d7eb951cd litedram (remotes/origin/HEAD) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a8b804809d84e2125eb603bf9feefc9cef31d22b litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 3e189379f9272ba184fcdcfe077eb139f1f0fc7f litex (heads/master) 657c0c72e63597162837809dfe3635d69a98cfd9 migen (0.6.dev-179-g657c0c7)

* edid-decode changed from 15df4ae to 42f5fa4 * 42f5fa4 - edid-decode: add comment w.r.t. JOC <Hans Verkuil> * a479a24 - edid-decode: parse additional flags in the DD+ Short Audio Descriptor <Arnaud Vrac> * litedram changed from 67de3ce to 6c53996 * 6c53996 - core/refresher: reduce refresh period by one cycle <Florent Kermarrec> * afb6d0a - core/refresher: reduce RefreshGenerator start delay by 1 cycle <Florent Kermarrec> * b543286 - test/test_refresh: add Refresher test <Florent Kermarrec> * 7daf355 - test/test_bist: remove vcd generation (only useful for debug) <Florent Kermarrec> * b4125fa - test/test_refresh: add RefreshTimer test <Florent Kermarrec> * 9584c2f - test: remove use of rand_wait, rename rand_level to random <Florent Kermarrec> * 0eef5d4 - test: add test_refresh with simple RefreshGenerator test <Florent Kermarrec> * 9348800 - test: rename test_timing_controllers to test_timing <Florent Kermarrec> * 8cf561d - test/test_timing_controllers: add simple tFAWController tests <Florent Kermarrec> * 3ae666d - test/test_timing_controllers: add simple tXXDController tests <Florent Kermarrec> * 394a49a - test: add test_timing_controllers with tXXDController test <Florent Kermarrec> * 6e3f769 - core: move timing controllers to common <Florent Kermarrec> * 54cdc7f - test: -x on tests <Florent Kermarrec> * 2ecb053 - frontend/ecc: move generic part of ECC to LiteX <Florent Kermarrec> * 8646b2e - test/test_adaption: use same DUT for up/down converter tests <Florent Kermarrec> * 9f9fed0 - test: merge test_downconverter/test_upconverter in a single test_adaptation file <Florent Kermarrec> * fc41751 - frontend/dma: simplify rsv_level expose <Florent Kermarrec> * 88835de - Merge pull request #86 from sergachev/master <enjoy-digital> |\ | * f145287 - dma: expose reservation level in the reader <Ilia Sergachev> |/ * f018c9e - add CONTRIBUTORS file and add copyright header to all files. <Florent Kermarrec> * 18dda2d - phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits <Florent Kermarrec> * 690e4f8 - README: fix ECP5 frequency ratio <Florent Kermarrec> * liteeth changed from 2424e62 to ad187d3 * ad187d3 - add CONTRIBUTORS file and add copyright header to all files <Florent Kermarrec> * fd6d6c3 - mac: update imports <Florent Kermarrec> * a170acd - change MAC location (next to phy/core/frontend), keep import retro-compatibility <Florent Kermarrec> * 789dadd - liteeth/software: remove libwip/libuip examples. <Florent Kermarrec> * litepcie changed from de6cd01 to 71c9a3a * 71c9a3a - core/tlp: rewrite controller (simplify, always enable reordering) <Florent Kermarrec> * 619f5c5 - add CONTRIBUTORS file and copyright header to all files. <Florent Kermarrec> * litesata changed from 6fe4cce to db5d2f7 * db5d2f7 - add CONTRIBUTORS and copyright header to all files. <Florent Kermarrec> * litescope changed from 2474ce9 to 9e3b9d8 * 9e3b9d8 - add CONTRIBUTORS file and add copyright header to all files. <Florent Kermarrec> * 66956cb - Merge pull request #13 from keesj/arty_fast_scope <enjoy-digital> * 144bd06 - Add an example of sampling at 800Mhz using a serdes on arty. <kees.jongenburger> * 7f4dc39 - Add functionality to flatten values that are sampled using a serdes. <kees.jongenburger> * liteusb changed from 0a9110f to 7457a29 * 7457a29 - README: deprecate, indicate new code location <Florent Kermarrec> * litex changed from 113f7f40 to e637aa65 * e637aa65 - Merge pull request timvideos#222 from antmicro/bump_vexriscv <enjoy-digital> |\ | * 932475a2 - cpu/vexriscv: bump submodule <Mateusz Holenko> |/ * bc7ab637 - bios/sdram: fix compilation warning <Florent Kermarrec> * a7895e49 - test/test_axi: remove use of rand_wait, rename rand_level to random <Florent Kermarrec> * 1cfb36e1 - soc_core: round memory regions size/length to next power of 2 (if not already a power of 2) <Florent Kermarrec> * 556d2c7c - Merge pull request timvideos#221 from antmicro/bump_vexriscv <enjoy-digital> |\ | * 3e89c564 - cpu/vexriscv: bump submodule <Mateusz Holenko> |/ * e673fce4 - bios/boot: fix default EMULATOR_RAM_BASE <Florent Kermarrec> * 0acacbaa - cores/clock: cleanup <Florent Kermarrec> * edf8aa8c - cores/clock: add initial iCE40 support <Florent Kermarrec> * 6d543358 - cores/spi_flash/add_clk_primitive: return if clk primitive is not needed <Florent Kermarrec> * 462d12ba - bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET <Florent Kermarrec> * fc12961e - soc_core: fix cpu_variant definition <Florent Kermarrec> * af61688d - bios/boot: fix booting rework <Florent Kermarrec> * 4b686dbd - soc_core: fix cpu_variant config (we don't want the extension) <Florent Kermarrec> * 7d9cf1d2 - Merge pull request timvideos#216 from antmicro/booting_vexriscv_linux <enjoy-digital> |\ | * 8335f13f - bios/boot: rework netboot/flashboot for VexRiscv in linux variant <Mateusz Holenko> | * a19bdd0e - soc_core: generate extra string-based config defines <Mateusz Holenko> | * 005c0776 - soc_core: include information about cpu variant in csv and headers <Mateusz Holenko> * | 95cfd0b9 - cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) <Florent Kermarrec> * | bfdcf4b2 - platforms/versa_ecp5: add spiflash pads <Florent Kermarrec> * | 41eb21b3 - soc_core: optimize mem_decoder <Florent Kermarrec> * | 0eff65bb - cores/up5ksram: optimize bus.adr decoding <Florent Kermarrec> * | bb99c468 - cores/up5kspram: simplify and add support for all width/depth configurations <Florent Kermarrec> * | eaf84b85 - cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional <Florent Kermarrec> * | ea619e3a - cores/spi: rename add_control paramter to add_csr <Florent Kermarrec> * | ec411a6a - soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs <Florent Kermarrec> * | bca42f74 - Merge pull request timvideos#219 from flammit/fix-ecp5-pll <enjoy-digital> |\ \ | |/ |/| | * c6c74391 - soc: cores: fix name of EHXPLLL output clock in ECP5PLL <Francis Lam> |/ * d3aaaf5e - cores/spi: fix/simplify loopback <Florent Kermarrec> * 59fda8da - README: update banner <Florent Kermarrec> * 769d15d4 - cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test <Florent Kermarrec> * ee8fec10 - soc/cores: add ECC (Error Correcting Code) <Florent Kermarrec> * 7dbddb3a - platforms/tinyfpga_bx: add serial extension <Florent Kermarrec> * 831a1916 - README: add a few links to papers/presentations/tutorials <Florent Kermarrec> * 95796c5b - Merge pull request timvideos#218 from railnova/zynq <enjoy-digital> |\ | * dcf55ad4 - [fix] Slave interface HP0 clk name <chmousset> * | 08772fc0 - Merge pull request timvideos#217 from sergachev/master <enjoy-digital> |\ \ | |/ |/| | * dacec6aa - spi: change CSR to CSRStorage <Ilia Sergachev> |/ * be280bed - soc_zynq: use zynq fabric reset as sys reset <Florent Kermarrec> * 220f4375 - soc_zynq: add missing axi hp0 clock <Florent Kermarrec> * 9c8c0371 - soc_zynq: move axi gp0 clock connection to add_gp0 method <Florent Kermarrec> * b0192e5f - soc_core: use fixed 16MB CSR address space <Florent Kermarrec> * 68a50317 - soc_sdram: limit main_ram to 512MB for now <Florent Kermarrec> * ccbf1418 - compiler-rt: update to new location, fixes timvideos#209 <Florent Kermarrec> * 21a5aaa4 - soc_core: declare csr address size when registering csr, fixes timvideos#212 <Florent Kermarrec> * 41b6fbde - soc_cores: fix typos <Florent Kermarrec> * bff081a8 - Merge pull request timvideos#214 from gsomlo/gls-alignment-fixup <enjoy-digital> |\ | * e42f33ed - soc_core: additional csr_alignment follow-up fixes <Gabriel L. Somlo> |/ * f4770219 - soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs <Florent Kermarrec> * 927b7c13 - soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) <Florent Kermarrec> * 96f45bbd - software/libbase/id: update code (length is now fixed to 256) <Florent Kermarrec> * 282ae963 - cores: add simple PWM (Pulse Width Modulation) module <Florent Kermarrec> * 77e7f9b3 - core/spi: make cs_n optional (sometimes managed externally) <Florent Kermarrec> * e726ad80 - cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) <Florent Kermarrec> * 4c18c991 - cores: add ICAP core (tested with reconfiguration commands) <Florent Kermarrec> * 6b82f23c - cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. <Florent Kermarrec> * ada70e8c - soc/cores/spi: remove too complicated and does not seem reliable in all cases. <Florent Kermarrec> * 7cd5c0f3 - cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging <Florent Kermarrec> * d29b8419 - cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) <Florent Kermarrec> * 3f6bd266 - cores/gpio: remove Blinker <Florent Kermarrec> * 359b8fe4 - Merge pull request timvideos#210 from DurandA/master <Tim Ansell> |\ | * 68eeba91 - Add verilog submodule from CPU cores to manifest <Arnaud Durand> |/ * 4ee9c53f - csr: add assert to ensure CSR size < busword (thanks tweakoz) <Florent Kermarrec> * 0116b2b7 - soc_core: update default RocketChip mem_map <Florent Kermarrec> * 9d170b09 - soc_core: rearrange default mem_map <Florent Kermarrec> * 05b667bb - bios/main: fix #ifdefs for fw command <Florent Kermarrec> * 37687579 - libnet/tftp: fix compilation warning <Florent Kermarrec> * 9f3c8a9b - bios/main: fix spiflash compilation warnings <Florent Kermarrec> * 2da59b29 - soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) <Florent Kermarrec> * b8d45af5 - targets: use new prefered way to add wishbone slave <Florent Kermarrec> * 7618b845 - soc_core: use new way to add wisbone slave (now prefered) <Florent Kermarrec> * 740629ba - soc_core: remove 256MB mem_map limitation <Florent Kermarrec> * b65968c3 - soc/core: remove #!/usr/bin/env python3 <Florent Kermarrec> * f49d0fe6 - Merge pull request timvideos#206 from gsomlo/gls-tftp-spinner <enjoy-digital> |\ | * 5a42dbf3 - BIOS: TFTP: ASCII spinner progress indicator (cosmetic) <Gabriel L. Somlo> |/ * d5177d72 - Merge pull request timvideos#204 from antmicro/write_to_flash <enjoy-digital> |\ | * 2ee194b2 - bios: add fw (flash write) command <Mateusz Holenko> * | cef23690 - core/spi_flash: re-integrate bitbang write support <Florent Kermarrec> |/ * 5cc4c334 - README: remove LiteUSB (deprecated) <Florent Kermarrec> * dc03b7fa - boards: community supported boards are now located at https://github.com/litex-hub/litex-boards <Florent Kermarrec> * 0af017e6 - liteeth: update mac imports (olds still works, but that's now the prefered way) <Florent Kermarrec> * ecf999b8 - soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB <Florent Kermarrec> * e667d5ae - README: update Intro <Florent Kermarrec> * 8f6e66ca - make sure #!/usr/bin/env python3 is before copyright header <Florent Kermarrec> * c7f36ab0 - test: add copyright header <Florent Kermarrec> * daa4307d - add CONTRIBUTORS file and add copyright header to all files <Florent Kermarrec> * 361f9d0d - bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) <Florent Kermarrec> * d8ac9362 - Convert top level comment to a docstring. <Tim 'mithro' Ansell> * 45632c66 - Merge pull request timvideos#202 from xobs/add-up5kspram <enjoy-digital> |\ | * 7656f54d - soc: cores: add up5kspram module <William D. Jones> |/ * 73dbffe8 - cores/frequency_meter: allow passing clk to be measured as a parameter <Florent Kermarrec> * 408d3f1f - Merge pull request timvideos#201 from gsomlo/gls-fix-initmem <enjoy-digital> |\ | * ab827d21 - tools/litex_sim: fix default endianness for mem_init <Gabriel L. Somlo> |/ * f47b4902 - Merge pull request timvideos#200 from gsomlo/gls-rocket-variants <enjoy-digital> |\ | * f75863fc - cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants <Gabriel L. Somlo> |/ * c0df9e08 - cpu/rocket: update submodule <Florent Kermarrec> * 87118d50 - integration/soc_core: move cpu_variant checks/formating to cpu <Florent Kermarrec> * f6b67a6d - cpu/vexriscv: add "linux+no-dsp" variant <Florent Kermarrec> * 95b1b454 - cpu/vexriscv: update <Florent Kermarrec> * e46d287b - targets/ulx3s: use CAS latency of 3 to be compatible with production boards <Florent Kermarrec> * litex-renode changed from bd1d0a0 to a57aa47 * a57aa47 - Merge pull request #8 from antmicro/newest_litex_fixes <Tim Ansell> |\ | * aebbe7f - Rework obtaining system clock frequency. <Mateusz Holenko> | * bd77b6c - Do not generate `csr` memory region. <Mateusz Holenko> |/ * 0d3b303 - Merge pull request #7 from antmicro/support_more_peripherals <Tim Ansell> * 406eafb - Fix generation of SPI flash peripheral. <Mateusz Holenko> * ab22e8f - Change VexRiscv configuration. <Mateusz Holenko> * f799d28 - Generate `cpu` (CPU timer) peripheral. <Mateusz Holenko> * c2bea62 - Allow to set custom interrupts. <Mateusz Holenko> * 66a4add - Allow to override the peripheral name. <Mateusz Holenko> * 409b696 - Generate `cas` (Control And Status) peripheral. <Mateusz Holenko> * ae3bee6 - Generate `ethphy` peripheral. <Mateusz Holenko> * migen changed from 0.6.dev-283-g562c046 to 0.6.dev-289-g5585912 * 5585912 - cdc: avoid race between data and request in BusSynchronizer <Sebastien Bourdeauducq> * f4979a2 - cdc: add BlindTransfer (from artiq.rtio.cdc) <Sebastien Bourdeauducq> * dd4ed5d - lattice/diamond: remove source/toolchain_path <Sebastien Bourdeauducq> * b0d9a18 - fix ISE build <Sebastien Bourdeauducq> * caab414 - build: remove tool version detection and sourcing of vendor script <Sebastien Bourdeauducq> * 5c5486b - xilinx: work around Vivado locale bug. Closes timvideos#183 <Sebastien Bourdeauducq> Full submodule status -- 42f5fa4ed99b669da4b4169a42eca7dbf5a293c7 edid-decode (remotes/origin/HEAD) 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master) 6c53996a7042050def908882b36e92585b6ef138 litedram (remotes/origin/HEAD) ad187d35f2b967eb152adcc9f1998a914e5bb53a liteeth (heads/master) 71c9a3a2eeaae8c4c44ffae14fb5417b94319206 litepcie (remotes/origin/HEAD) db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master) 9e3b9d84ce6d0e895d0ac275df78ccbd0e0e0ab2 litescope (heads/master) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master) e637aa657b7c1163c7c21c4b972f4aa947406272 litex (remotes/origin/HEAD) a57aa47ff6863f08d75d33fb5545ea489817ac0d litex-renode (remotes/origin/HEAD) 558591288dd08302cb8830310ba6975757b58c72 migen (0.6.dev-289-g5585912)

Bump third_party/litex from e07bd7 to dcae61

809def5

Bumps [third_party/litex](https://github.com/enjoy-digital/litex) from e07bd7 to dcae61. - [Commits](enjoy-digital/litex@e07bd71...dcae61b)

dependabot-preview bot added the dependencies label Nov 2, 2017

dependabot-preview bot mentioned this pull request Nov 2, 2017

Bump third_party/litex from e07bd7 to 2665a8 #10

Closed

dependabot-preview bot closed this Nov 9, 2017

dependabot-preview bot deleted the dependabot/submodules/third_party/litex-dcae61 branch November 9, 2017 07:11

mithro added a commit that referenced this pull request Jan 19, 2018

Merge pull request #13 from ewen-naos-nz/arty-micropython-firmware

237e723

arty: Support "make firmware-load" for F=micropython

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Bump third_party/litex from e07bd7 to dcae61 #13

Bump third_party/litex from e07bd7 to dcae61 #13

dependabot-preview bot commented Nov 2, 2017

dependabot-preview bot commented Nov 9, 2017

Bump third_party/litex from e07bd7 to dcae61 #13

Bump third_party/litex from e07bd7 to dcae61 #13

Conversation

dependabot-preview bot commented Nov 2, 2017

dependabot-preview bot commented Nov 9, 2017