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ISE generates both working and non-working firmware from the same input verilog #209
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The current theory is that we are missing timing constraints needed to make sure the encoder (or something related to the encoder) to no longer work. |
This issue might be related to the following issues;
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@jordens created the following LD_PRELOAD to try and make ISE more deterministic. https://github.com/jordens/unrandom |
Credit should go to @whitequark. |
Random comment I found from https://forums.xilinx.com/t5/Welcome-Join/Multiple-Seed-Place-amp-route/td-p/503024
See See also https://www.fpgarelated.com/showthread/comp.arch.fpga/46386-1.php |
A fix for the prj file generation can be found in timvideos/migen@c468315 |
With the current issue in #227 you get the following
S == files that are the same The mem.init and mem_3.init are different because of #228 |
This PDF contains the command line arguments for the Xilinx tools which might be useful for figuring out what is going on. |
The output of the first step is the ngc file ( |
ISE is currently generating both working and non-working firmware from the same git commit to the repo.
Version v0.0.0-606-gebbfdc5 was built twice on Travis, the first version fails to produce valid JPEG frames, the second version kind of works.
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