Introduce collected hardware changes for ulx3s #88
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For some ancient reason, Seg7 (some of the oldest Verilog code in this project) was readable without a clock edge. This will prevent good inference of memories, and is unnecessary, so read out on a clock edge only. (Reading out of Seg7 is not even a particularly necessary behavior, and could be removed entirely at some point.)
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During the implementation of #87 for #49, some changes to the hardware description were needed. The current PR collects those changes separately.