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Merge pull request #88 from kulp/hw-changes-for-ulx3s
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Introduce collected hardware changes for ulx3s
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@kulp
kulp committed Jun 30, 2021
2 parents 6afd300 + 746aedb commit ea81d27
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36 changes: 18 additions & 18 deletions hw/verilog/hex2segments.v
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@@ -1,26 +1,26 @@
`include "common.vh"
`timescale 1ns/10ps

module Hex2Segments(input clk, input[3:0] hex, output reg[6:0] seg);
module Hex2Segments(input[3:0] hex, output reg[6:0] seg);

always @(posedge clk)
always @*
case (hex)
4'h0: seg <= 7'b1000000;
4'h1: seg <= 7'b1111001;
4'h2: seg <= 7'b0100100;
4'h3: seg <= 7'b0110000;
4'h4: seg <= 7'b0011001;
4'h5: seg <= 7'b0010010;
4'h6: seg <= 7'b0000010;
4'h7: seg <= 7'b1111000;
4'h8: seg <= 7'b0000000;
4'h9: seg <= 7'b0010000;
4'ha: seg <= 7'b0001000;
4'hb: seg <= 7'b0000011;
4'hc: seg <= 7'b1000110;
4'hd: seg <= 7'b0100001;
4'he: seg <= 7'b0000110;
4'hf: seg <= 7'b0001110;
4'h0: seg = 7'b1000000;
4'h1: seg = 7'b1111001;
4'h2: seg = 7'b0100100;
4'h3: seg = 7'b0110000;
4'h4: seg = 7'b0011001;
4'h5: seg = 7'b0010010;
4'h6: seg = 7'b0000010;
4'h7: seg = 7'b1111000;
4'h8: seg = 7'b0000000;
4'h9: seg = 7'b0010000;
4'ha: seg = 7'b0001000;
4'hb: seg = 7'b0000011;
4'hc: seg = 7'b1000110;
4'hd: seg = 7'b0100001;
4'he: seg = 7'b0000110;
4'hf: seg = 7'b0001110;
endcase

endmodule
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2 changes: 1 addition & 1 deletion hw/verilog/ram.v
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@@ -1,7 +1,7 @@
`include "common.vh"
`timescale 1ns/10ps

module BlockRAM(
module TwoPortRAM(
clka, ena, wea, clkb, enb, web, acka, ackb,
addra, dina, douta, addrb, dinb, doutb
);
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20 changes: 10 additions & 10 deletions hw/verilog/seg7.v
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Expand Up @@ -2,16 +2,17 @@
`timescale 1ns/10ps

// basic 7-segment driver
module Seg7(clk, strobe, rw, reset, addr, d_in, d_out, seg, an);
module Seg7(clk, strobe, ack, rw, reset, addr, d_in, d_out, seg, an);

parameter CNT_BITS = 16 + 2; // 80MHz clk => 2ms full screen refresh
localparam DIGITS = 4;
parameter DIGITS = 4;

input wire clk, strobe, rw, reset;
input wire [31:0] addr, d_in;
output reg [31:0] d_out;
output wire[ 7:0] seg;
output wire[DIGITS-1:0] an;
output reg ack;

reg[CNT_BITS-1:0] counter = 0;
reg[DIGITS*4-1:0] store;
Expand All @@ -20,7 +21,7 @@ module Seg7(clk, strobe, rw, reset, addr, d_in, d_out, seg, an);
wire[1:0] dig = counter[CNT_BITS - 2 +: 2];
assign seg[7] = (dots[0 +: 4] & ~an) == 0;
assign an = ~(1 << dig);
Hex2Segments lookup(clk, store[dig * 4 +: 4], seg[6:0]);
Hex2Segments lookup(store[dig * 4 +: 4], seg[6:0]);

always @(posedge clk) begin
if (reset) begin
Expand All @@ -29,23 +30,22 @@ module Seg7(clk, strobe, rw, reset, addr, d_in, d_out, seg, an);
dots <= 0;
end else begin
counter <= counter + 1;
ack <= strobe;
if (strobe) begin
if (rw) begin
case (addr[0])
1'b0: store <= d_in[DIGITS*4-1:0];
1'b1: dots <= d_in[3:0];
endcase
end else begin
case (addr[0])
1'b0: d_out <= {16'b0,store};
1'b1: d_out <= {28'b0,dots};
endcase
end
end
end
end

always @* begin
case (addr[0])
1'b0: d_out = {16'b0,store};
1'b1: d_out = {28'b0,dots};
endcase
end

endmodule

5 changes: 3 additions & 2 deletions hw/verilog/tenyr.v
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Expand Up @@ -93,15 +93,15 @@ module Core(
inout halt
);

localparam[3:0] s0=0, s1=1, s2=2, s3=3, s4=4, s5=5, s6=6;
localparam[3:0] s0=0, s1=1, s2=2, s3=3, s4=4, s5=5, s6=6, s7=7;

wire deref_rhs, branching, storing, loading, edone;
wire[3:0] idxX, idxY, idxZ, op;
wire signed[31:0] valX, valY, valZ, valI, valA, valB, valC, rhs;
wire[1:0] kind;
reg[31:0] insn, _data;
reg signed[31:0] _irhs, nextP;
reg[3:0] state = s5;
reg[3:0] state;

wire signed[31:0] nextI = branching ? nextZ : nextP;
wire signed[31:0] nextZ = deref_rhs ? _data : _irhs;
Expand Down Expand Up @@ -130,6 +130,7 @@ module Core(
s4: begin state <= s5 ; adr_o <= nextI; end
s5: begin state <= ack_i ? s6 : s5; nextP <= adr_o + 1; end
s6: begin state <= s0 ; insn <= dat_i; end
s7: begin state <= s5; end
endcase

Decode decode(.insn, .op, .idxZ, .idxX, .idxY, .valI, .deref_rhs,
Expand Down
20 changes: 10 additions & 10 deletions hw/verilog/top.v
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Expand Up @@ -3,8 +3,8 @@

module Tenyr(
input clk, reset, inout halt,
output[7:0] Led, output[7:0] seg, output[3:0] an, inout[23:0] gpio,
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync
output[7:0] seg, output[3:0] an, inout[23:0] gpio,
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync, inframe
);

parameter LOADFILE = "default.memh";
Expand All @@ -18,7 +18,6 @@ module Tenyr(
wire[31:0] d_adr, d_to_slav, i_to_slav;
wire[31:0] d_to_mast, i_to_mast;

assign Led[7:0] = {8{halt}};
assign i_ack = i_stb;

tenyr_mainclock clocks(
Expand Down Expand Up @@ -49,11 +48,11 @@ module Tenyr(
wire[3:0] r_sel;
wire[31:0] r_adr, r_ddn, r_dup;

BlockRAM #(.LOADH(1), .LOADFILE(LOADFILE), .INIT(0),
TwoPortRAM #(.LOADH(1), .LOADFILE(LOADFILE), .INIT(0),
.PBITS(32), .ABITS(RAMABITS), .OFFSET(`RESETVECTOR)
) ram(
.clka ( clk_core ),
.ena ( r_stb ),
.clka ( clk_core ), .clkb ( 1'b0 ),
.ena ( r_stb ), .enb ( 1'b0 ),
.acka ( r_ack ),
.wea ( r_wen ),
.addra ( r_adr ),
Expand All @@ -77,15 +76,15 @@ module Tenyr(
);
`endif

wire g_wen, g_stb, g_cyc;
wire g_wen, g_stb, g_cyc, g_ack;
wire[3:0] g_sel;
wire[31:0] g_adr, g_ddn, g_dup;
wire g_stbcyc = g_stb & g_cyc;

Seg7 seg7(
.clk ( clk_core ), .rw ( g_wen ), .seg ( seg ),
.reset ( reset ), .addr ( g_adr ), .an ( an ),
.strobe ( g_stbcyc ), .d_in ( g_ddn ), .d_out ( g_dup )
.strobe ( g_stbcyc ), .d_in ( g_ddn ), .d_out ( g_dup ), .ack( g_ack )
);

wire o_wen, o_stb, o_cyc;
Expand All @@ -110,7 +109,8 @@ module Tenyr(
.clk_vga ( clk_vga ), .addr ( v_adr ), .vgaGreen ( vgaGreen ),
.en ( 1'b1 ), .d_in ( v_ddn ), .vgaBlue ( vgaBlue ),
.reset ( reset ), .d_out ( v_dup ), .hsync ( hsync ),
.strobe ( v_stbcyc ), .vsync ( vsync )
.strobe ( v_stbcyc ), .vsync ( vsync ),
.inframe ( inframe )
);
`endif

Expand Down Expand Up @@ -147,7 +147,7 @@ module Tenyr(
.wbs_we_o ({ o_wen, g_wen, v_wen, s_wen, r_wen, x_wen }),
.wbs_sel_o ({ o_sel, g_sel, v_sel, s_sel, r_sel, x_sel }),
.wbs_stb_o ({ o_stb, g_stb, v_stb, s_stb, r_stb, x_stb }),
.wbs_ack_i ({ o_stb, g_stb, v_stb, s_stb, r_ack, x_stb }),
.wbs_ack_i ({ o_stb, g_ack, v_stb, s_stb, r_ack, x_stb }),
.wbs_err_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_rty_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_cyc_o ({ o_cyc, g_cyc, v_cyc, s_cyc, r_cyc, x_cyc }),
Expand Down
13 changes: 4 additions & 9 deletions hw/verilog/vga_text.v
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Expand Up @@ -51,7 +51,7 @@ endmodule

module vga_text(
/* input */ reset, clk, TEXT_D, FONT_D,
/* output */ R, G, B, hsync, vsync, TEXT_A, FONT_A
/* output */ R, G, B, inframe, hsync, vsync, TEXT_A, FONT_A
);

parameter integer ScrnCols = 640;
Expand Down Expand Up @@ -90,6 +90,8 @@ module vga_text(
assign hsync = ~hsync_p; // need negative polarity
assign vsync = ~vsync_p; // need negative polarity

output wire inframe = state == sActive;

reg [3:0] state = sInit;

// TODO change to integers
Expand Down Expand Up @@ -158,18 +160,11 @@ module vga_text(
.out(vsync_p)
);

// This delay is empirical and needs to be explained
wire active_delayed;
shift_reg #(.LEN(FontCols)) active_delay(
.clk(clk), .en(1), .in(active),
.out(active_delayed)
);

always @(posedge clk) begin
TEXT_A <= trow * TextCols + tcol;
FONT_A <= TEXT_D * FontRows + frow;
pixels <= Width_done ? FONT_D : pixels >> 1;
W <= pixels & active_delayed & 1;
W <= pixels & active & 1;

case (state)
sActive: state <= Active_done ? sHFront : sActive; // ^ ^
Expand Down
8 changes: 4 additions & 4 deletions hw/verilog/vgawrap.v
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Expand Up @@ -4,7 +4,7 @@
module VGAwrap(
input clk_core, clk_vga, en, rw, reset,
input strobe, input[31:0] addr, input[31:0] d_in, output wor[31:0] d_out,
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync, inframe
);

parameter[31:0] VIDEO_ADDR = `VIDEO_ADDR;
Expand All @@ -23,10 +23,10 @@ module VGAwrap(
.R ( vgaRed[2] ), .G ( vgaGreen[2] ), .B ( vgaBlue[2] ),
.hsync ( hsync ), .vsync ( vsync ),
.TEXT_A ( ram_adA ), .TEXT_D ( ram_doA ),
.FONT_A ( rom_adA ), .FONT_D ( rom_doA )
.FONT_A ( rom_adA ), .FONT_D ( rom_doA ), .inframe,
);

BlockRAM #(
TwoPortRAM #(
.SIZE(ROWS * COLS), .ABITS($clog2(ROWS * COLS) + 1), .DBITS(8), .INIT(1), .ZERO('h20)
) text(
.clka ( clk_vga ), .clkb ( clk_core ),
Expand All @@ -37,7 +37,7 @@ module VGAwrap(
.wea ( 1'b0 ), .web ( rw )
);

BlockRAM #(.LOADB(1), .LOADFILE("../../rsrc/font10x15/rev.font10x15.memb"),
TwoPortRAM #(.LOADB(1), .LOADFILE("../../rsrc/font10x15/rev.font10x15.memb"),
.SIZE(256 * FONT_ROWS), .DBITS(FONT_COLS))
font(
.clka ( clk_vga ), .ena ( 1'b1 ), .wea ( 1'b0 ),
Expand Down

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