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2020 09 28 sync
Alexey Bader edited this page Sep 29, 2020
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Opens
- 2020 LLVM Dev Meeting round table agenda.
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Patches in review for llorg:
- https://reviews.llvm.org/D87282 - [SYCL] Assume SYCL device functions are convergent
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https://reviews.llvm.org/D80932 - [SYCL] Make default address space a superset of OpenCL address spaces
- https://reviews.llvm.org/D62574 - Add support for target-configurable address spaces.
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GitHub issues/PRs
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https://github.com/intel/llvm/issues/1799#issuecomment-637395726 -
half
implementation:__fp16
vs_Float16
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https://github.com/intel/llvm/issues/2041 - [SYCL][FE] Add an attribute to annotate special sycl types
- https://reviews.llvm.org/D71016 - [SYCL] Implement OpenCL kernel function generation
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https://github.com/intel/llvm/issues/1799#issuecomment-637395726 -
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Back-burner
- https://reviews.llvm.org/D77220 - [SYCL] Enable OpenCL types required for implementing the SYCL headers.
Participants: Alexey Bader (Intel), Mariya Podchischaeva (Intel), Michael Wong (Codeplay), Victor Lomuller (Codeplay), Gauthier Harnisch (Xilinx), Ronan Keryell (Xilinx)
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Opens
- 2020 LLVM Dev Meeting round table agenda topics:
- SYCL address space attributes implementation
- SPIR-V translator library upstream.
- It's critical part of the device compiler.
- Check if MLIR community is interested in unifying SPIR-V support in the long run.
- Upstreaming SYCL runtime and libclc modifications.
- 2020 LLVM Dev Meeting round table agenda topics:
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Patches in review for llorg:
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https://reviews.llvm.org/D87282 - [SYCL] Assume SYCL device functions are convergent
- Need reviewers.
- Victor: the change makes sense to me
- Alexey: I'll add Victor as a reviewer
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https://reviews.llvm.org/D80932 - [SYCL] Make default address space a superset of OpenCL address spaces
- https://reviews.llvm.org/D62574 - Add support for target-configurable address spaces.
- Alexey: I'm working on rebasing our old patch adding new attributes for SYCL address spaces
- Alexey: Need to fix lit test failures
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https://reviews.llvm.org/D87282 - [SYCL] Assume SYCL device functions are convergent
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GitHub issues/PRs
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https://github.com/intel/llvm/issues/1799#issuecomment-637395726 - half implementation: __fp16 vs _Float16.
- test https://github.com/intel/llvm/pull/2000 on ToT.
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https://github.com/intel/llvm/issues/2041 - [SYCL][FE] Add an attribute to annotate special sycl types
- https://reviews.llvm.org/D71016 - [SYCL] Implement OpenCL kernel function generation
- Ronan: can we pass the structure as is + parameters requiring decomposition (e.g. sampler).
- Mariya: we had something like this in the past. There are two issues with this: it violates OpenCL/SPIR specs and make it hard to analyze due to argument copy.
- Roland: Another problem is whether spec allows inherit and/or wrap structs with sampler/accessors, etc.
- Mariya: to check if https://github.com/intel/llvm/pull/2091 can re-use an attribute added by https://github.com/intel/llvm/commit/15e62c2d0e23839224661d4f8a4e291720dd401c.
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https://github.com/intel/llvm/issues/1799#issuecomment-637395726 - half implementation: __fp16 vs _Float16.